Talent 101 Circuit

IC Design Engineer with Layout Experience Available

Posted on February 17, 2017 by Kent Smith

Jose – IC Design Engineer

  • Oversaw development of all power management IP (Buck, Boost, LDOs) and other analog IP (GPADC, PLL)
  • Oversaw Floor-planning and module layout development
  • Managed customer interaction to make sure alignment was maintained on technical and project aspects
  • Designed boot regulator to allow switch to be brought above input voltage to improve RdsOn
  • Designed Frequency fold-back circuit to modify clock frequency – used to prevent over-current fault
  • Built >3.5GHz Divider circuit in a 90nm process
  • Took existing design and increased the speed from 2GHz and enabled to output 50% duty cycle
  • Developed I/O cells to support but 1.2V and 1.8V operation from a single design
  • Participated in loop design for Low jitter PLL
  • Built group’s first high voltage charge pump in bipolar process to enable improve level shifter performance (switch impedance)
  • Combined B.S./M.S – Electrical and Computer Engineering

Topics: Semiconductor News, Design Engineer

Kent Smith

Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.