Marina – IC Layout Design Engineer
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Proficiency in LVS, DRC, DFM, ERC with Hercules VUE (Synopsys), Caliber (MentorG).
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Experience in CADENCE layout tools, Virtuoso & Virtuoso Layout-XL.
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Working knowledge and self-sufficient in UNIX terminal operations.
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In-depth knowledge in full custom layout design in 16nm(12LM), exposure to 7nm(14M).
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Well versed with advanced layout techniques, dual patterning, G0 rules, voltage DRCs, metal coloring, LOD effects, WPE, PODE, DNW, Analog matching techniques, parasitics reduction, High speed RF Layout design, Floor planning from leaf cells, block level placement and integration, Noise isolation, Latch-up issues in IO designs, High current designs, creating robust Decap structures, Power grid planning, Density fixes, Coupling issues on analog/HF signals, RC matching on critical areas with custom density fills, minimizing IR drops, EM fixes, robust ESD & POWER clamps connections.
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Hands on experience in Virtuoso XL using advanced techniques to create fast and good quality layouts, maintain schematic connectivity for easy review with circuit designer.
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Worked on SKILL CAD, advanced layout supporting utility.
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RF, Analog, Standard cell and High-speed layout design.
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Deep knowledge in analyzing and resolving Antenna, Latch Up, ESD and IR drop issues.
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Working experience on multiple hierarchy layout designs spread across multiple teams.
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Good problem-solving and teamwork skills along with strong verbal and written communication skills.
