Talent 101 Circuit

Srikanth – Electrical Engineer  

• Academic experience in ASIC/ SoC RTL Design (with Verilog HDL and System Verilog) and Functional Verification.
• Hands-on experience of RTL Logic Synthesis, Static Timing Analysis (STA), Power Analysis and Optimization
• VLSI Proficiency:  ASIC and FPGA Design flow, Physical Design flow (Floor planning, Placement, CTS and Routing), Physical Verification, Signal Integrity and CMOS IC Design, Characterization, Simulation and Layout
• Languages:  Verilog HDL, System Verilog, C/ C++ (Object Oriented) Programming, Perl Scripting, UNIX Shell Scripting
• EDA Tools:  Synopsys VCS, Synopsys DC,  Cadence NC-Verilog, Cadence Virtuoso, Cadence SOC Encounter, SPICE, ModelSim-Altera, Altera Quartus II, MATLAB, Atmel Flip  
• Protocols:  UART, I2C, SPI and AMBA – APB, AHB and AXI
• Lab Equipment:  Digital Oscilloscope, Power Supplies, Logic Analyzers, Bus Analyzers
• Master of Science, Electrical Engineering