Talent CIRCUIT (32)

Lab Technician with Verification Testing Experience

Posted on August 15, 2017 by Kent Smith

Benny – Lab/Bench Technician

Performs engineering tests, checkouts, and development engineering tasks.
Diagnoses and isolates malfunctions to the component level.
Analyzes engineering test results, and implements changes to resolve problems.
Conducts operations tests and fault isolation on development systems and equipment to ensure conformance with design specifications, collecting data, analyzing results and implementing procedures.
Verification testing of electrical hardware, software, and systems level.

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Product Engineer Available

Posted on August 10, 2017 by Kent Smith

Kaveen – Engineering Project Manager / Product Engineer

Efficient deployment of playbook process and requirements across Product Line
Management of full product lifecycle from Assess to Ramp.
Trained 2 PE rotation candidates to complete 2x AEC qualification (3 lots Quals)
Led 3 RTM’s in 2016 – Functional Safety Automotive device

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Layout Engineer Available

Posted on August 08, 2017 by Kent Smith

Janice – Analog AMS Layout Engineer

Created custom layouts for LDOs Power Controller, LFO, HFO, and REF_SYS.
Floorplan, module interconnect, power routing and quality assurance of top level blocks
Created custom high voltage layouts for Oscillators, Current References, Charge Pumps, Voltage Regulators and various other cells used in the Flash Charge Pump

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FPGA Developer Expert Available

Posted on August 04, 2017 by Kent Smith

Nathan – FPGA Developer/Scripting Expert (Available Immediately)

Writes/debugs Python based firmware test programs for a new device, including battery.
Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
Responsible for the ROM contents on Veridian. Additionally responsible for the new Flash programming and erase routines for the customer. Develops random test bench to exercise the Flash memory.

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Senior Product Development Engineer

Posted on July 31, 2017 by Kent Smith

Tomas – Sr. Product Development Engineer

10+ years’ experience in all phases of semiconductors and PCBA full cycle development engineering using various analog/digital statistical analysis
Measurement instrumentation
Various ATE platforms plus standalone bench test equipment to test RF cellular and WLAN Systems, Ethernet L2, L3 protocols, PCIe, mixed signal and analog embedded MCU chips with embedded ARM microcontrollers

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Analog IC Power Designer Available

Posted on July 26, 2017 by Kent Smith

Gopi – Analog IC Power Designer (Available immediately)

Detailed circuit design including circuit blocks such as Buck/Boost, Charge Pump, ADC etc.
Integration of circuit blocks into a top-level design.
Detailed simulation including worst case analysis and statistical analysis.
Top level simulation and design verification.
Guidance to layout and review of layouts for accuracy and optimum performance.
Simulation with extracted parasitic elements to verify performance of actual layout.
Present results to the TI product team.

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Experienced Physical Designer Engineer Available

Posted on July 24, 2017 by Kent Smith

Kane – Physical Design Engineer

Physical Design
Block level Implementation and physical design of various blocks for 7nm processor.
Synthesis, place and route, timing, clock tree synthesis, scan chain. IR and EM study and fixes. DRC, LVS clean up
Execution Unit
Fetch Unit
Memory Subsystem

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Qual & Test Technician Available

Posted on July 18, 2017 by Kent Smith

Kita – Qual & Test Technician

Testing and colleting of data of semiconducting devices on a multi-test handler
Assembling customer samples for use in prototype devices
Characterization of temperature data during stress testing
Recording and inputting test data on share drives

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System Validation Engineer with Python Experience Available

Posted on July 13, 2017 by Kent Smith

Sue – System Validation Engineer

Tested/Validated the features such as power management, multimedia framework
Developed Python functional test script based on all the requirements. The script can run on Windows client and Beagle Bone Black host/Linux (Debian) to communicate with test equipment, EVM through serial/DeVaSys/I2C.
Perform validation test including functional test and hardware timing
Review schematic with other design engineers.
Develop in house user guide and complete system installation procedure.
Document the weakness of the system and work around.
Developed Python stress test script and perform functional testing on system. The test included LABB, 3D, CAIC, Keystone, TPG, mode transition, etc.
Git/Mercurial is being used for script software version control and JIRA for bug tracking.
Review requirement document to validate the software, hardware timing requirement and DLP tool.
Attend regular review meeting to monitor the JIRA progress to ensure issue being resolved

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Senior Circuit Design Engineer Available

Posted on July 11, 2017 by Kent Smith

Pete – Senior Circuit Design Engineer

Physical Design
Mixed-Signal Design
Project Management
SOC Encounter
RTL to GDS
Static Timing Analysis
Circuit Simulation

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