Talent 101 Circuit

Physical Design Engineer Available

Posted on October 07, 2016 by Kent Smith

Srikanth – Physical Design Engineer

  • Contracting position at Texas Instruments, as part of physical design team, worked closely with digital and analog teams to deliver design on time under tight schedule.
  • Worked on diversified designs of high utilizations, irregular shapes, and complex clock tree structure with Encounter Foundation Flow based TI methodology.
  • Applied SDP, which allow easy and quick manipulation of delay cell block based on block shape.
  • Worked on timing signoff of SSD controller SOC, TSMC 40nm.
  • Compared timing results among tapeout.
  • IBM 40nm i32soi, worked on stretched version of HMC.
  • Per customer requirement, die is stretched in Y direction: -800 um and +800 um.
  • Worked on top level timing closure.
  • Bump placement, place bumps with various patterns, assign signals to bumps.
  • Floorplan, pin placement, RAM placement, power meshes, analog block placement.
  • Clock tree generation using ccopt.
  • Worked on timing analysis/closure at both top and block level.

Topics: Design Engineer

Kent Smith

Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.

kents@talent-101.com