Talent 101 Circuit

Senior Design Verification Engineer with experience in Mixed Signal Design

Posted on April 16, 2018 by Kent Smith

Harold – Senior Design Verification Engineer

  • Design Verification – Constrained Random Full Chip & Unit Level SoC, ASIC, & FPGA
  • System Verilog/UVM
  • Functional Coverage & Code Coverage
  • Assertion (SVA) Based Verification
  • Verilog, VHDL
  • VCS, IUS, QuestaSim, Verdi
  • Python, TCL & PERL Scripting
  • Test Bench Architecture & Implementation
  • Verification Planning & Scheduling
  • Revision Control SVN, Design Sync, Perforce, GIT, RCS, CVS
  • C/C++, C#, Assembly
  • Ethernet, PCI, SPI, AHB, DDR4, Bus Protocols
  • Transmission Line Modeling & Analysis
  • Analog Behavioral Modeling in SPICE
  • Mixed Signal Circuit Design
  • Hardware Design
  • Exceptional Communication Skills
  • Training & Mentorship – Group & Individual
  • Technical Leadership

Contact Us About This Candidate

Topics: Design Engineer, Verification Engineer

Kent Smith

Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.