Alezandro – Senior Digital Design/Verification Engineer
- 10+ years’ experience with Verilog RTL design including nine years with System Verilog design and verification.
- Experienced in CMOS integrated circuit design/verification at RTL and transistor levels.
- Custom and RTL-based design/verification projects include: MIPS and ARM-based SoCs, X86 CPU, 8/16-bit microcontrollers, DSP processor and custom CMOS memory design (Flash, SRAM, and ROM).
- Design/CAD tool experience:
- Cadence: NC-Sim (Verilog/System Verilog), SimVision, HSPICE, Verplex
- Mentor Graphics: Questa (Verilog/System Verilog), VHDL
- Synopsys: VCS, Nanosim, Debussy/Verdi, Formality, SpyGlass, MATLAB
- HDL, System and Scripting language experience: Verilog/System Verilog, C/C++, Perl, Python, Ruby, Csh
- System Verilog Verification Methodologies: UVM, OVM, OVL, SVA
- MSEE in Digital Systems
Topics:
Verification Engineer,
Digital Design
Nick Trompert
Nick Trompert is a Sr. Manager. He is responsible for connecting with the best engineering and information technology talent and resources in the world. He is one of the founders of Talent 101 and joined full time after college.
nickt@talent-101.com
