Jerry – Senior FPGA/ASIC Designer
- Logic design and verification, behavioral modeling and analog mixed-signal simulation and debug skills. Expertise in Verilog and VHDL coding, functional verification, synthesis, timing analysis, and micro architecture. Wrote and ran regression tests using TCL.
- Wrote VHDL and Verilog for DSP libraries and simulated these functions using MODELSIM.
- Wrote Perl programs to run all the VHDL and Verilog simulations.
- Logic Design/Verification (15 yrs.), RTL coding (10 yrs.), Verilog (10 yrs.), VHDL (10 yrs.).
- Analog Mixed-signal Simulation (Using SPICE and ModelSim) (18 years), UNIX (14 yrs.).
- Experience with ASIC DFT.
- CAE/EDA TOOLS EXPERIENCE: XILINX Vivado and ISE Design tools. SYNOPSYS: PRIMETIME, DESIGN COMPILER, VHDL, VERILOG, PSPICE, VCS, VSS. MODELSIM, CVS, VIEWLOGIC: POWERVIEW, MENTOR: QUICKSIM, MSPICE.
- SOFTWARE: TCL, Perl, C, C++, UNIX shell scripts.
- DESIGN: PCIe Interface, Digital video camera, MPEG-2 encoder, ISDN, 8 and 16 Microprocessor control system, I/O Interface, digital controller. ASIC CMOS, FPGA (Altera, Xilinx, Quick logic and Chip Express) and Analog power supplies.
- TEST EQUIPMENT: Logic analyzer, Analog & Digital oscilloscope, vector impedance meter, power supply, DMM, signal generators, spectrum analyzer.
Topics:
Design Engineer
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
