Vanu – Senior Layout Designer Engineer
- Proficient with SiGe process as IBM bicmos 8hp, 9hp. TOWER-JAZZ bicmos Ha, H3, and TSMC process as 16 nano, 20 nano, 40, 60, 90 etc.
- Perform layout of high-speed VGA, TIA, LDO, OpAmp, Bias, Clamp, ADC, DAC, Power Generation, RF amplifiers, Detectors, Filters, Oscillators, etc.
- Module generated, synchronized clone with virtuoso up to date Cadence v6.16.
- High performance layout Electro migration, IR drop, ESD, Latchup.
- Ability to layout analog circuitry in a size/time constrained environment.
- Understand layout techniques such as common centroid, matching, isolation, shielding, and the use of dummy devices.
- Ability to solve design problems while using a combination of technical skills, intuition, and creativity.
- Troubleshooting layout design issues and applying proactive intervention.
- Proficiency in floor planning activities with block assembly, and block level routing.
- LVS trouble shooting and debug skills.
- Familiar with Assura and Calibre verify tool such as DRC, ERC, ESD, Density, Latch up, ANT and LVS.
- Layout design of high precision analog / mixed signal circuits subject to multiple constraints.
- Debug LVS/DRC/ERC errors with verification tool.
Topics:
Design Engineer
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
