Maria– Senior Layout Engineer
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Senior IC Layout Designer/Leader with strong people, team-building, and project management skills
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Lead Layout Designer, for new Rad Hard Microwave 10GHZ designs.
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Utilizing SiGe IBM, HP for RF circuitry (TX, RX) etc
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Created various IP in 45nm blocks
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Trained on the new 10nm FinFET process
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Performed layout on various FinFET Macros
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Utilizing bicmos 8HP- 90nm, and cms 9flp-130nm for RF Circuitry.
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Currently kicking off new 14nm FinFET IBM projects for various new designs
