Talent 101 Circuit

Janie – Senior Design Engineer

• ASIC Design Flow, FPGA Design
• RTL Design (Verilog, VHDL)
• Test Benching
• Simulation & Verification
• Cadence (NC), Synopsys VCS

• Timing and waveform analysis for debug
• Timing closure using reports
• Adept at learning new tools
• MS Word, Excel, Visio, PowerPoint
• Verilog, VHDL
• MS Access
• VBA (Visual Basic for Applications)
• UNIX, TCL, C, Scripting
• SQL (Standard Query Language)
• C & C# Languages, PHP, HTML
• MVC 2.0 & ASP.Net
• Some JAVA, jQuery, Json, Ajax, CSS Script, LINQ
• QuickBooks, Peachtree
• BSEE Degree