Thie – System Engineer
- Experience as a System Engineer with excellent critical thinking and programming skills
- Programming/Scripting/Debugging: C/C++ (Object Oriented), bash, csh, Tcl, PERL, Python, GNU debugger
- Hardware Description Languages: VHDL, Verilog, System Verilog. UVM basics
- Behavioral Simulation Tools: Icarus Verilog, ModelSim, Synopsys VCS, NC Verilog and NCSim
- Experience in ASIC Flow, FSM/RTL Design and Synthesis, Timing Analysis, RTL and Gate-level Verification
- Academic knowledge of BUS Models: I2C, SPI, PC/AT, AMBA AHB and APB, AXI, PCI, PCIe
- Synthesis EDA tools: Synopsys Design Compiler (dc shell and design vision)
- FPGA Tools: Xilinx ISE and Vivado, Altera Quartus. Place and Route Tools: Cadence Encounter
- Operation Systems: UNIX, Linux (Ubuntu and Fedora), Windows
- MS in Electrical Engineering
