Amith - Verification Designer in ASIC / FPGA / SOC
- 15 years of experience in all phases of ASIC/ FPGA/ SOC Design/Verification
- A strong track record of successfully verifying and delivering complex FPGAs/ASICs/SOCs to production with first pass silicon successes
- Building complete UVM based test bench environments from scratch.
- Developing Drivers, Monitors, Sequencers, Agents, Scoreboards, Checkers.
- Architecture, Micro-architecture Specification, RTL Design and Coding using Verilog / VHDL Simulation, and Debug.
- Logic Synthesis, Static Timing Analysis, Timing Closure, BIST/Scan Insertion, DFT design
