Ganti – Verification Engineer
- 10+ years of experienced in digital design and verification.
- Designed micro-controllers, protocol controllers (multi-channel HDLC, AMI), DRAM.
- controller, DSP functions (IIR/FIR filters, digital gain blocks, companders, DTMF generator), uP interfaces, serial interfaces and JTAG interface.
- Written high level functions/behavioral models of ISDN S/T analog interface, DSP functions of CODEC, DTMF generator, SBus, ISA bus and memory elements.
- Experience with verification of GPIO, ARM, DDR and Flash interfaces.
- Experienced using RTL simulators (VSC, Nc-verilog, Modelsim), synthesis (DC), timing (PT), equivalence checkers (formality), fault simulators, UVM functional coverage (scoreboards), assertions (bindfiles) and UVM covergroups, lint analysis, and code coverage (Atrenta/Spyglass) tools.
- Experience using AMS and System Verilog based OVM/UVM.