Padu – Verification Engineer
- Verification Engineer with 15+ years of experience specializing in digital verification, functional validation, full chip simulations, System Verilog development, test bench development.
- Full-chip DFX functional validation.
- Write and debug full-chip test patterns for Low Power UPF simulations and HVM
- Test plan creation, review and execution.
- Writing System Verilog.
- Technical driver Low Power x86 CPU - full-chip directed stimulus porting.
- Doctor of Philosophy in Electrical Engineering.
Topics:
Verification Engineer
Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
kents@talent-101.com
