Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
Sham - Senior Verification Engineer
- 8yrs+ overall industry experience in Mixed Signal and Digital Verification
- Experience in System Verilog and UVM, PSL, and SVA Assertions
- Behavioral Modeling of Analog Modules in SV, VAMS, and VHDL
- Model Vs. Spice Simulations, Analog Mixed Signal Co-Simulations
- Verification of Sound wire, I2C, AHB, and DMA protocols
- Functional and Code coverage Analysis
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Jay – Physical Design/Digital Back end Engineer (Available Immediately)
- Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule.
- Working on complex digital on top lower power design.
- Define and verify power intent.
- RTL synthesis.
- Equivalence check.
- Floorplan.
- Define power domain and power routing.
- Insert power switches.
- Isolation and retention cells placement.
- CTS and routing.
- STA timing analysis.
- Worked on top level timing closure.
- Bump placement, place bumps with various patterns, assign signals to bumps.
- Floorplan, pin placement, RAM placement, power meshes, analog block placement.
- Clock tree generation using ccopt.
- Worked on timing analysis/closure at both top and block level.
- Worked on diversified designs of high utilizations, irregular shapes, and complex clock tree structure with Encounter Foundation Flow.
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Ariel – FPGA Developer/Scripting Expert (Available Immediately)
- Writes/debugs Python-based firmware test programs for a new device, including battery.
- Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
- Responsible for the ROM contents on Veridian. Additionally responsible for the new Flash programming and erase routines for the customer. Develops random test bench to exercise the Flash memory.
- Wrote a python emulator of the Veridian device. The ARM cortex M0+ core was modelled along with RAM, ROM, FLASH, UART and other blocks. The emulator reads the ELF file containing the binary code compiled by the Keil tools and provides a near clock accurate execution model of that code running on Veridian. This enables the Veridian ROM image to be debugged in advance of Silicon.
- Developed a flash emulation on a FPGA. Through a ROM based C program, emulates the Flash API library to allow the Veridian customer to develop their firmware on a FPGA with confidence that it will function on the silicon when it is finished.
- Developed a Verilog AMS generator to interface the digital and analog portions of Veridian together. This enabled the design team to simulate concurrently the digital and analog design databases.
- Developed a Verilog generator that instantiates the level shifters between the different power domains on Veridian. The Python programs reads an Excel spreadsheet to get a template and then generates a Verilog netlists as per that template.
- MSEE, Purdue University, GPA: 5.9/6.0
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Jared – Analog/Mixed Signal Design Engineer
- Analog, mixed signal, and high-performance RF IC design.
- Switching power converters, LDOs, DC/DC, Buck and Boost, and Power ICs.
- Hall sensors for automotive industries.
- Analog interface circuits for MRAM, DDR interface.
- Ultra-high accuracy CMOS frequency references with mitigated aging.
- High-performance RF IC Design and Analog/Mixed Signal IC Design.
- State-of-art low-noise and low distortion RF/analog front-ends.
- Wireless transceiver system design, video-receivers and mass-storage channels.
- IC subsystem design: PLL’s, DDL’s, gain-controls and gm-C filters.
- CMOS, BiCMOS and bipolar IC block design such as: LNAs, mixers, phase shifters, amplifiers, comparators, PAs, VCOs, charge pumps, ADCs, DACs, LDOs, power supplies, and bias blocks.
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Kevin– Analog/Mixed Signal Design Engineer
- Buck, Boost, LDO, Regulators ADC
- 1.2V buck converter, 50mA output
- 3.3V boost converter, 150mA output
- Current-limited voltage source for PoDL detect circuit.
- Sense chopper amplifier for PoE.
- Audio codec Development
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Ayobe – Manufacturing Mechanical Engineer
- Mechanical Engineering
- Process Development
- Operational Reliability
- Process Control/Reengineering
- Component Testing
- Regulatory Compliance
- Project Management
- Contract Administration
- Operations/Maintenance
- Designing and implementing cost effective solutions within complex R&D
- Pilot scale and manufacturing environments for commercial and governmental organizations
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RICO – HARDWARE/FIRMWARE ENGINEER (AVAILABLE IMMEDIATELY)
- Writes/debugs Python based firmware test programs for a new device, including battery.
- Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
- Responsible for the ROM contents on Veridian. Additionally responsible for the new Flash programming and erase routines for the customer. Develops random test bench to exercise the Flash memory.
- Wrote a python emulator of the Veridian device. The ARM cortex M0+ core was modelled along with RAM, ROM, FLASH, UART and other blocks. The emulator reads the ELF file containing the binary code compiled by the Keil tools and provides a near clock accurate execution model of that code running on Veridian. This enables the Veridian ROM image to be debugged in advance of Silicon.
- Developed a flash emulation on a FPGA. Through a ROM based C program, emulates the Flash API library to allow the Veridian customer to develop their firmware on a FPGA with confidence that it will function on the silicon when it is finished.
- Developed a Verilog AMS generator to interface the digital and analog portions of Veridian together. This enabled the design team to simulate concurrently the digital and analog design databases.
- Developed a Verilog generator that instantiates the level shifters between the different power domains on Veridian. The Python programs reads an Excel spreadsheet to get a template and then generates a Verilog netlists as per that template.
- MSEE, Purdue University
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Honorio – Test/Qual Technician
- Conducted hand-screening of prototype IC units on ATE and bench EVM platforms to support customer sample demand.
- Specialized in high-throughput testing of smaller package sizes, including WCSP packages on the order of 1.5 mm dimension.
- Such hand activity routinely involved quantities in the thousands at rates ranging from 100 units per hour to 500 units per hour, and demanded innovation of customized testing approaches and apparatus.
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Vidal - Layout Engineer
- Perform chip level physical Analog Custom Layout design using latest Cadence Virtuoso Layout Editor VLE/VXL layout tools and techniques for optimization of speed, power, and area (.35um & .7um technologies).
- Excellent device matching techniques along with debug and verification ability at device, cell, block, and chip levels.
- Verify correctness and integrity of layout using expert checking (hierarchical) skills using DIVA and Calibre for DRC/Extraction/LVS/ERC/Antenna Checks.
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Abramo – Electronics & RF Technician
- Hands-on experience installing, testing, calibrating, designing, replacing and troubleshooting complex, military grade electronics and circuits.
- Strong knowledge of digital, analog, and RF electronics to the Gigahertz range, expert in the testing and troubleshooting of digital, analog, and RF components, circuit card assemblies and higher level units and systems that are used in military products and platforms and performing diagnostics and troubleshooting down to the component level.
- Highly proficient at supporting team leads and senior engineers with test operations, including the setup of test apparatus and conducting tests of electronic assemblies and units following defined methods, procedures, standards, and sequences and clearly and concisely documenting results.
- Can read, interpret and implement schematics, system flow diagrams, blueprints, BOMs, publications, wire lists, engineering orders, mechanical drawings, safety manuals, pre-task plans, maintenance plans, and Cleanroom, 5/6S, SCIFs, Lean principles, PPE, HAZMAT, lockout/tagout, 6D (Decon/Demo), FOD, and security protocols.
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