Kent Smith
Kent Smith is a Senior Business Development Manager at Talent 101. He is responsible for managing the semiconductor engineering solutions at Talent 101’s clients. His expertise includes recruiting and workforce solutions, and working with engineering groups at Talent 101’s clients to improve business performance.
Jeffrey – Design Verification Engineer
- Extensive experience in the Design Verification in both block and SoC levels
- Skilled in directed and constrained-random test benches
- Proficient in Object-Oriented programming
- Languages – System Verilog, Verilog, SVA, C, Perl, Shell Scripts, assembly (e200, e500, HC08, HC12)
- Verification methodologies – UVM, VMM
- Simulators – VCS, NC Verilog (incisive), Verilog XL
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Maribel – Senior ASIC/SOC Design/Verification Engineer
- ASIC Firmware/Hardware Integration
- ASIC / SOC Development & Design & Methodology implementation
- Experienced project lead in hard drive controller support.
- ASIC/SOC Conceptual & Layout Design
- Verilog, VDHL, Perl, RTL, UNIX, embedded coding; some OOP C++ and Python.
- Drove/supported clock Generator, SOC Clock Timing, and IDDQ analysis.
- CPU and microarchitectures
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Sostenes – FPGA Design Engineer
- 8 Years of strong experience in FPGA/ASIC design and verification flow, Architecture, RTL coding, Functional Verification, Synthesis, Gate level simulations, Static timing analysis (STA), ATPG
- Experience in the design of Xilinx Zynq-7000 Soc, Spartan3E, Lattice LFXP2-40E, and LFXP2-30E & Altera Cyclone III FPGA Boards
- Good Knowledge of ASIC design tools and process flow
- Proficient with C/C++, Verilog HDL, VHDL and System Verilog
- Good knowledge of simulation tools Cadence, Questasim, & Active
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Samantha – Design Verification Engineer
- Design Verification Engineer with experience in defining testbench architecture, verification planning, and implementation in UVM.
- Knowledge of UVM Environment - Agents (Sequencer, Driver, Monitor), test writing/debug and Coverage.
- Formal Verification, Assertion-based verification.
- Strong knowledge of developing Stimulus, Verification flow, Digital Design, UVM, and OOP.
- Proficient in developing Monitors, Checkers, and Scoreboards in System Verilog.
- Experience on UNIX/LINUX, PERL, Verilog.
- Master of Science in Electrical Engineering
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Lui – Physical Design Engineer
- Physical design engineer with experience in mixed-signal circuit design.
- Experienced in all phases of circuit / physical design including synthesis, static timing analysis, optimization, and implementation.
- Experienced in technical project management, high-speed memory design (SRAM), and design flow development.
- Physical Design, Mixed-Signal Design, Project Management, SOC Encounter and RTL to GDS
- Static Timing Analysis, Circuit Simulation, Synthesis, Spectre/MDL and EMIR
- Magma, Virtuoso, ICC, HSPICE and Cadence
- TCL, Synopsys, Primetime, RTL Compiler and ASIC
- B.S. in Electrical Engineering
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Scree – Physical Design Engineer [Available April 15, 2018]
- 5 years’ experience
- Floor planning, placement, Clock Tree Synthesis, Routing
- Physical optimization - timing, power, area
- Static Timing Analysis signoff, power analysis
- Physical hardening of complex sub-designs
- Top level design planning, I/O placements, and full-chip closure.
- Signal integrity analysis
- Design Rule checks, Logic equivalence checks
- Design automation using scripting language
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Kumar – Senior VLSI Engineer [Available May 1, 2018]
- 7yrs overall industry experience – IP verification (RTL and GLS), FPGA verification and RTL Design.
- Experience in Digital Verification (testbench environment, models, checkers, drivers, functional coverage, assertions and test case development in system Verilog and Verilog languages).
- Experience in using scripting languages like Perl for pre/post-processing of results.
- Experience in Verilog, SV and UVM test bench environments.
- Experience in RTL design.
- Experience in different serial and parallel bus protocols.
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Ali – Analog Layout Design Engineer
- 10+ years’ experience
- Experience working on Optical, Voice and Memory chips
- Experience with both Chip and Block level work
- DAC, Controller, Bi-CMOS, CMOS, LDO, PLL, ADC
- Global Foundries, TSMC, Xfab Processes
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Ramesh - Senior VLSI Design Engineer
- Five years of experience as Physical Layer IP Team lead, contributed mainly as Lead Designer.
- Contributed to multiple activities from Pre-sales to Silicon bring up of PHY IPs.
- Eleven years of Career in semiconductor field covering Design, Synthesis, STA, FPGA, DFT.
- Excellent in defining timing constraints including tight Analog to Digital interface signals.
- Performed STA for 6 Projects.
- Good combination of strong design skills with in depth timing visualization.
- Verilog RTL designer with experience in Multi Clock Domain Designs.
- Expertise in SOC level and IP level DFT Design, Verification and Silicon testing including DC and at speed scan, Memory BIST.
- Closely works with STA / PnR team to address challenging timing / area closures, ECOs.
- Performed design evaluation in Xilinx FPGAs.
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Vinod – AMS Engineer
- 10+ years of experience in Analog, Mixed Signal and High-speed IO Layout Design of modules and Chip level tasks.
- Worked on various technology nodes like 180nm, to 10nm
- Proficient in layout design using Cadence Virtuoso XL and Genesys
- Custom layout design of blocks, IPs and Full Chip Integration
- Floor planning, Power planning and Area estimation of modules
- Special planning during placement considering density, HV,EMIR,DRC in deep submicron nodes
- Physical Verification of the layout designs
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