Talent 101 Circuit

Norma – Engineering Test Technician  

• Responsible for product testing of ADS548X analog to digital converters
• Created Bin summary
• Fail analysis using Data power and Spotfire
• Provided support to Test Engineers by data acquisition, failure analysis, qualification testing, soldering and desoldering IC on PCBs, sample testing, characterization, product qualification testing, extracting data from Test ware Data Extraction, test board verifications, monitors production and yield percentage
• Generated reports for Engineers using Microsoft Powerpoint and Microsoft Excel

Zak – Senior Engineering/Test Technician

• RF Characterization
• Gallium Nitride RF FETs, Wafers, and fixtured devices
• Load pull – calibration 12 Benches including Mesuro, Focus, and Maury Microwave
• S-parameters - Agilent Precision Network Analyzer to 67 & 110GHz
• RF Power measurements
• Various DC Tests- Pulsed IV, DC Transfer, And Three Terminal Breakdown
• Collect and analyze laboratory data and prepare circuit characterization reports for modeling and qualification
• Test fixture design and fabrication-AutoCAD, Bridgeport mill, Lathe, Drill press, band saw
• Under minimal supervision
• Lab Management duties 

Joshua – System Engineer 

• Design and engineering experience with commercial, military and space grade RF and Microwave hardware, including frequency sources, power amplifiers, mixers, filters and passive components.
• Characterized, simulated, tested, screened, and improved numerous designs employing mixed signal technology resulting in world-class products.
• Design Software:  NI LabVIEW, Multisim, AutoCAD, Cadence OrCAD PSPICE & Schematic Capture, Allegro HDL, Agilent Genesys, Agilent Advanced Design Software (ADS), AnsoftHFSS, Operating Systems, Windows 2000/XP/Vista/7, UNIX
• Programming Languages:  MATLAB, C/C++

Shiva – Physical Design Engineer 

• Physical Design Engineer in the field of Semiconductor design.
• Experienced in ASIC design flow from RTL to GDSII: RTL Synthesis, Floor Planning, Power Planning, Placement and trail routing, CTS, Routing, Parasitic Extraction, STA & SI, and DRC/LVS.
• Hands on experience in RTL design and verification of digital design using Verilog.
• Proficient scripting skills in Perl, TCL, and Shell.
• M.S. in Electrical Engineering

Barbara – Senior ASIC Physical Design Engineer 

• 20+ years as a physical designer and 10 tape-outs, from netlist to GDS
• 10+ years of methodology development, understanding and using other company’s methodology
• VLSI design work & custom layout using backend tools from Synopsys(ICC1), Cadence(Innovus)
• Large 28 million gate design, physical partition into three blocks. Intel 10nm process and library and IP
• Create and developed a power estimate to create IR/EM correct power rails using Synopsys tools for TSMC flow
• Extensive use of portable scripting languages for tools flow development
• Versed in Microsoft EXCEL spreadsheet for calculations

Charbel – Physical Design Engineer 

• Core experience centered on physical design of large complex CMOS, ASIC, SOC Designs using industry standard tools i.e. Innovus, ICC, talus, and Primetime.
• Responsible for synthesis, formal verification, floor planning (block and top level), power creation and repair, timing driven placement and routing, CTS, timing convergence and analysis, noise convergence and analysis, LVS and DRC.
• Proficient in Cadence's SOC FE, Synopsys' ICC and talus performing synthesis, place and route, timing closure and power analysis.
• Intermediate user of Mentor’s Olympus tool. 
• Proficient user of PTSI from Synopsys and Calibre performing LVS/DRC. 

Harold – Senior Design Verification Engineer

• Design Verification – Constrained Random Full Chip & Unit Level SoC, ASIC, & FPGA
• System Verilog/UVM
• Functional Coverage & Code Coverage
• Assertion (SVA) Based Verification
• Verilog, VHDL
• VCS, IUS, QuestaSim, Verdi
• Python, TCL & PERL Scripting
• VERA/RVM
• Test Bench Architecture & Implementation

Chang – Design Verification Engineer

• High-performance IC/ASIC design and verification.  
• Co-author of two patents.  Strong critical thinking, problem-solving, and planning skills.
• Expert in UVM, System Verilog, VHDL. 
• Experienced in developing and deploying new verification methodologies. 
• Proven track record of developing and delivering high-quality designs on time. 
• Strong leadership and collaboration skills.
• Outstanding team player, mentor, and coach.
• Engineering & Product Management.

Shae – Quality Assurance Test Engineer

• Goal Oriented Quality Assurance Test Engineer with diverse experience in Manual & Automation testing.
• Solid knowledge of software development lifecycle and software testing life cycle.
• Excellent written/oral communication and strong leadership skills. Possess analytical, troubleshooting and problem-solving skills.
• Able to work independently and in a Team environment.
• Worked on Projects with Java Advanced level (Web-based P
  rojects) and on Embedded systems.

Roger – Quality Engineer

• Quality and process engineering knowledge along with positive perspective and effective problem-solving techniques.
• Creates innovative solutions, driving consistent results and improving revenue and growth.
• Inspires the respect and confidence of team members and leaders, while remaining keenly aware of organizational growth initiatives and the company’s potential to meet customer needs.
• Successfully establishes knowledge of Quality Management System and drives for compliance with customer and company requirements, as well as evaluates the risk of new products and processes.
• Develops, executes and documents projects in compliance with committed timelines and project goals.
• Master of Science in Management of Technology.