Talent 101 Circuit

Lathan – FPGA Developer/Scripting Expert (Available Immediately)

• Writes/debugs Python based firmware test programs for a new device, including battery.
•  Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
• Responsible for the ROM contents on Veridian. Additionally responsible for the new Flash programming and erase routines for the customer. Develops random test bench to exercise the Flash memory.

Fang – Physical Design/Digital Back end Engineer 

Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule

• Working on complex digital on top lower power design
• Define and verify power intent
• RTL synthesis
• Equivalence check
• Floorplan
• Define power domain and power routing

Mickey – Analog IC Power Engineer

• Detailed circuit design including circuit blocks such as Buck/Boost, Charge Pump, ADC etc.
• Integration of circuit blocks into a top-level design.
• Detailed simulation including worst case analysis and statistical analysis.
• Top level simulation and design verification.

Keta – Qual & Test Technician

• Testing and collecting of data of semiconducting devices on a multi-test handler
• Assembling customer samples for use in prototype devices
• Characterization of temperature data during stress testing
• Recording and inputting test data on share drives
• Downloading and converting data from Test Ware

Benny – Lab/Bench Technician

• Performs engineering tests, checkouts, and development engineering tasks.
• Diagnoses and isolates malfunctions to the component level.
• Analyzes engineering test results, and implements changes to resolve problems.
• Conducts operations tests and fault isolation on development systems and equipment to ensure conformance with design specifications, collecting data, analyzing results and implementing procedures.
• Verification testing of electrical hardware, software, and systems level.

Kaveen – Engineering Project Manager / Product Engineer

• Efficient deployment of playbook process and requirements across Product Line
• Management of full product lifecycle from Assess to Ramp.
• Trained 2 PE rotation candidates  to complete 2x AEC qualification (3 lots Quals)
• Led 3 RTM’s in 2016 – Functional Safety Automotive device  

Janice – Analog AMS Layout Engineer

• Created custom layouts for LDOs Power Controller, LFO, HFO, and REF_SYS.
• Floorplan, module interconnect, power routing and quality assurance of top level blocks
• Created custom high voltage layouts for Oscillators, Current References, Charge Pumps, Voltage Regulators and various other cells used in the Flash Charge Pump

Nathan – FPGA Developer/Scripting Expert (Available Immediately)

• Writes/debugs Python based firmware test programs for a new device, including battery.
•  Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
• Responsible for the ROM contents on Veridian.  Additionally responsible for the new Flash programming and erase routines for the customer.  Develops random test bench to exercise the Flash memory.

Tomas – Sr. Product Development Engineer  

• 10+ years’ experience in all phases of semiconductors and PCBA full cycle development engineering using various analog/digital statistical analysis
• Measurement instrumentation
• Various ATE platforms plus standalone bench test equipment to test RF cellular and WLAN Systems, Ethernet L2, L3 protocols, PCIe, mixed signal and analog embedded MCU chips with embedded ARM microcontrollers

Gopi – Analog IC Power Designer (Available immediately)

• Detailed circuit design including circuit blocks such as Buck/Boost, Charge Pump, ADC etc.
• Integration of circuit blocks into a top-level design.
• Detailed simulation including worst case analysis and statistical analysis.
• Top level simulation and design verification.
• Guidance to layout and review of layouts for accuracy and optimum performance.
• Simulation with extracted parasitic elements to verify performance of actual layout.
• Present results to the TI product team.