Talent 101 Circuit

Kane – Physical Design Engineer  

• Physical Design
• Block level Implementation and physical design of various blocks for 7nm processor.
• Synthesis, place and route, timing, clock tree synthesis, scan chain.  IR and EM study and fixes.  DRC, LVS clean up
• Execution Unit
• Fetch Unit
• Memory Subsystem

Kita – Qual & Test Technician

• Testing and colleting of data of semiconducting devices on a multi-test  handler
• Assembling customer samples for use in prototype devices
• Characterization of temperature data during stress testing
• Recording and inputting test data on share drives

Sue – System Validation Engineer 

• Tested/Validated the features such as power management, multimedia framework
• Developed Python functional test script based on all the requirements. The script can run on Windows client and Beagle Bone Black host/Linux (Debian) to communicate with test equipment, EVM through serial/DeVaSys/I2C.
• Perform validation test including functional test and hardware timing
• Review schematic with other design engineers.
• Develop in house user guide and complete system installation procedure.
• Document the weakness of the system and work around.
• Developed Python stress test script and perform functional testing on system. The test included LABB, 3D, CAIC, Keystone, TPG, mode transition, etc.
• Git/Mercurial is being used for script software version control and JIRA for bug tracking.
• Review requirement document to validate the software, hardware timing requirement and DLP tool.
• Attend regular review meeting to monitor the JIRA progress to ensure issue being resolved

Pete – Senior Circuit Design Engineer  

• Physical Design
• Mixed-Signal Design
• Project Management  
• SOC Encounter
• RTL to GDS
• Static Timing Analysis
• Circuit Simulation

Nicholas – Design Verification Engineer  

• Extensive experience in the Design Verification at both block and SoC levels.
• Skilled in directed and constrained-random test benches.  Proficient in Object-Oriented programming.  
• Languages – System Verilog, Verilog, SVA, C, Perl, shell scripts, assembly (e200, e500, HC08, HC12).
• Verification Methodologies – UVM, VMM.
• Simulators – VCS, NC Verilog (Incisive), Verilog XL.

Kanti – Qual Tech - Eagle, V93K, Flex (Available Immediately)

Customer Sample Screening: 

• Conducted hand-screening of prototype IC units on ATE and bench EVM platforms to support customer sample demand. 
• Specialized in high-throughput testing of smaller package sizes, including WCSP packages on the order of 1.5 mm dimension. 
• Such hand activity routinely involved quantities in the thousands at rates ranging from 100 units per hour to 500 units per hour, and demanded innovation of customized testing approaches and apparatus.

Utfred – HW (ARM/FPGA) Design/Verification Validation Engineer 

• Testing and colleting of data of semiconducting devices on a multi-test  handler
• Assembling customer samples for use in prototype devices
• Characterization of temperature data during stress testing

 Mariska – System Validation Engineer   

• Developed Python functional test script based on all the requirements. The script can run on Windows client and BeagleBone Black host/Linux (Debian) to communicate with test equipment, DLPC2607 EVM through serial/DeVaSys/I2C.
• Perform validation test including functional test and hardware timing on DLPC2607/BeagleBone Black (Pico Display Light Crafter).

Joshua – Qual & Test Technician

• Testing and colleting of data of semiconducting devices on a multi-test  handler
• Assembling customer samples for use in prototype devices
• Characterization of temperature data during stress testing
• Recording and inputting test data on share drives
• Downloading and converting data from Test Ware 
• Creating graphs and histograms from Data Power
• Troubleshooting programs and test boards
• Improve test flow and production
• Completion of  TWR’s and QTS jobs

Fang – Physical Design/Digital Back end Engineer (available July 1, 2017)

Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule