Harry – IC Layout Design Engineer
- Custom layout of cells, IP blocks, and chips; including, where appropriate, floor planning, power planning, Analog/Digital custom layout, physical verification, and extraction.
- Place and Route of IP and at Chip Level; including floor planning, power planning and routing, Placement (based on one or more of the following Timing, Power, Clocks, Regions and Groups, Routing density), Clock tree synthesis, Custom Analog routing (Shielding, RC matching, and keep out areas), Detail routing, ECO, layout verification (DRC/ERC/LVS/Antenna/Density/LVL), and extraction.
- Group management; Schedule, methodology, and standards development.