Talent 101 Circuit

Kevin– Analog/Mixed Signal Design Engineer

• Buck, Boost, LDO, Regulators ADC
• 1.2V buck converter, 50mA output
• 3.3V boost converter, 150mA output
• Current-limited voltage source for PoDL detect circuit.
• Sense chopper amplifier for PoE.
• Audio codec Development

 Ayobe – Manufacturing Mechanical Engineer

• Mechanical Engineering
• Process Development
• Operational Reliability
• Process Control/Reengineering
• Component Testing
• Regulatory Compliance
• Project Management
• Contract Administration
• Operations/Maintenance
• Designing and implementing cost effective solutions within complex R&D
• Pilot scale and manufacturing environments for commercial and governmental organizations

RICO – HARDWARE/FIRMWARE ENGINEER (AVAILABLE IMMEDIATELY) 

• Writes/debugs Python based firmware test programs for a new device, including battery.
• Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
• Responsible for the ROM contents on Veridian. Additionally responsible for the new Flash programming and erase routines for the customer. Develops random test bench to exercise the Flash memory.
• Wrote a python emulator of the Veridian device. The ARM cortex M0+ core was modelled along with RAM, ROM, FLASH, UART and other blocks. The emulator reads the ELF file containing the binary code compiled by the Keil tools and provides a near clock accurate execution model of that code running on Veridian. This enables the Veridian ROM image to be debugged in advance of Silicon.
• Developed a flash emulation on a FPGA. Through a ROM based C program, emulates the Flash API library to allow the Veridian customer to develop their firmware on a FPGA with confidence that it will function on the silicon when it is finished.
• Developed a Verilog AMS generator to interface the digital and analog portions of Veridian together. This enabled the design team to simulate concurrently the digital and analog design databases.
• Developed a Verilog generator that instantiates the level shifters between the different power domains on Veridian. The Python programs reads an Excel spreadsheet to get a template and then generates a Verilog netlists as per that template.
• MSEE, Purdue University

Honorio – Test/Qual Technician

• Conducted hand-screening of prototype IC units on ATE and bench EVM platforms to support customer sample demand.
• Specialized in high-throughput testing of smaller package sizes, including WCSP packages on the order of 1.5 mm dimension.
• Such hand activity routinely involved quantities in the thousands at rates ranging from 100 units per hour to 500 units per hour, and demanded innovation of customized testing approaches and apparatus.

Vidal - Layout Engineer

• Perform chip level physical Analog Custom Layout design using latest Cadence Virtuoso Layout Editor VLE/VXL layout tools and techniques for optimization of speed, power, and area (.35um & .7um technologies).
• Excellent device matching techniques along with debug and verification ability at device, cell, block, and chip levels.
• Verify correctness and integrity of layout using expert checking (hierarchical) skills using DIVA and Calibre for DRC/Extraction/LVS/ERC/Antenna Checks.

Abramo – Electronics & RF Technician

• Hands-on experience installing, testing, calibrating, designing, replacing and troubleshooting complex, military grade electronics and circuits.
• Strong knowledge of digital, analog, and RF electronics to the Gigahertz range, expert in the testing and troubleshooting of digital, analog, and RF components, circuit card assemblies and higher level units and systems that are used in military products and platforms and performing diagnostics and troubleshooting down to the component level.
• Highly proficient at supporting team leads and senior engineers with test operations, including the setup of test apparatus and conducting tests of electronic assemblies and units following defined methods, procedures, standards, and sequences and clearly and concisely documenting results.
• Can read, interpret and implement schematics, system flow diagrams, blueprints, BOMs, publications, wire lists, engineering orders, mechanical drawings, safety manuals, pre-task plans, maintenance plans, and Cleanroom, 5/6S, SCIFs, Lean principles, PPE, HAZMAT, lockout/tagout, 6D (Decon/Demo), FOD, and security protocols.

Annette – Quality Engineer

• Databases SQL Server, Oracle, Hibernate
• Testing JUnit, Selenium, Cobertura, EasyMock, MockObjects
• Identity Management CA IdentityMinder, RedHat Directory Server
• Application Security CA SiteMinder (CA SSO), LDAP
• Continuous Integration Jenkins, Maven
• Code Analysis Tools PMD, FindBugs, CheckStyle, SonarQube
• Programming Languages JAVA, JSP, JSF, Java EE
• Content Management Adobe Experience Manager
• Architecture Java, Enterprise Design Patterns, Test Driven Development
• Application Servers Weblogic 10.1, 10.3, 11G, JBoss EAP 6, Apache, Tomcat
• Java Tools/Technologies Eclipse, J2EE, Struts, JDBC, JMS, JAXB, EJB, JSF 2.0

Julian - Physical Design Engineer

• More than 10 years as a Physical Design Engineer to tape out various products from SOC like Ethernet, Serdes, to RF/Mixed Signal chips like Bluetooth, NFC, touch screens, AD/Da etc.

• Taped out with various processes like 28nm, 45nm, 65nm, 90nm, 130nm, 180nm and foundries like TSMC, UMC, IBM, Charter, X-FAB, Jazz Semiconductors etc.

• More than 10 years as physical design CAD for the flow development, support and trains

• A track record of Project Leadership on large SOC implementations like 48 million gate Serdes switcher to small project like touch screen sensor
  

Erasmo - Quality Engineer

• Quality Engineering with expertise in Supplier, Manufacturing, Process, Customer Quality, Product Engineering, Electrical Engineering and Application Engineering
• Extensive experience in Aerospace, military grade electronic systems, automotive electronics, semiconductor manufacturing and MEMS sensors and their applications
• Led a highly effective engineering team in a fast paced contract manufacturing company
• Experience includes both Build to Print and initial prototype design development, design for EMC compliance, circuit board layout design direction and failure analysis of prototype designs and existing production assemblies

Norma – Physical Design Engineer

• Performed RTL Synthesis, Physical implementation through floor planning, auto place and route, clock tree synthesis and static timing analysis at 22nm

• Developed automated scripts using TCL, Perl with EDA tools to fix different violations like maxcap, maxtran, hold, setup and DRC
• Improved test coverage results by 25% by developing testability flow for three EDA tools and managed eight design automation tools
• Worked closely with tool vendors for technology specific feature enhancements for advanced Intel node process
• Documented tool usage procedures, prepared training documents and presented information to customers
• Managed and executed assigned design section of a micro server chip project using Synopsys tools