Talent CIRCUIT (28)

Physical design engineer experienced in mixed-signal design

Posted on March 28, 2018 by Kent Smith

Lui – Physical Design Engineer

Physical design engineer with experience in mixed-signal circuit design.
Experienced in all phases of circuit / physical design including synthesis, static timing analysis, optimization, and implementation.
Experienced in technical project management, high-speed memory design (SRAM), and design flow development.
Physical Design, Mixed-Signal Design, Project Management, SOC Encounter and RTL to GDS
Static Timing Analysis, Circuit Simulation, Synthesis, Spectre/MDL and EMIR
Magma, Virtuoso, ICC, HSPICE and Cadence
TCL, Synopsys, Primetime, RTL Compiler and ASIC
B.S. in Electrical Engineering

Physical Design Engineer with 5+ years experience

Posted on March 26, 2018 by Kent Smith

Scree – Physical Design Engineer [Available April 15, 2018]

5 years’ experience
Floor planning, placement, Clock Tree Synthesis, Routing
Physical optimization - timing, power, area
Static Timing Analysis signoff, power analysis
Physical hardening of complex sub-designs
Top level design planning, I/O placements, and full-chip closure.
Signal integrity analysis
Design Rule checks, Logic equivalence checks
Design automation using scripting language

Experienced Senior VLSI Engineer Available

Posted on March 23, 2018 by Kent Smith

Kumar – Senior VLSI Engineer [Available May 1, 2018]

7yrs overall industry experience – IP verification (RTL and GLS), FPGA verification and RTL Design.
Experience in Digital Verification (testbench environment, models, checkers, drivers, functional coverage, assertions and test case development in system Verilog and Verilog languages).
Experience in using scripting languages like Perl for pre/post-processing of results.
Experience in Verilog, SV and UVM test bench environments.
Experience in RTL design.
Experience in different serial and parallel bus protocols.

Analog Layout Design Engineer with 10+ Years experience

Posted on March 21, 2018 by Kent Smith

Ali – Analog Layout Design Engineer

10+ years’ experience
Experience working on Optical, Voice and Memory chips
Experience with both Chip and Block level work
DAC, Controller, Bi-CMOS, CMOS, LDO, PLL, ADC
Global Foundries, TSMC, Xfab Processes

Senior VLSI Design Engineer Available NOW

Posted on February 05, 2018 by Kent Smith

Ramesh - Senior VLSI Design Engineer

Five years of experience as Physical Layer IP Team lead, contributed mainly as Lead Designer.
Contributed to multiple activities from Pre-sales to Silicon bring up of PHY IPs.
Eleven years of Career in semiconductor field covering Design, Synthesis, STA, FPGA, DFT.
Excellent in defining timing constraints including tight Analog to Digital interface signals.
Performed STA for 6 Projects.
Good combination of strong design skills with in depth timing visualization.
Verilog RTL designer with experience in Multi Clock Domain Designs.
Expertise in SOC level and IP level DFT Design, Verification and Silicon testing including DC and at speed scan, Memory BIST.
Closely works with STA / PnR team to address challenging timing / area closures, ECOs.
Performed design evaluation in Xilinx FPGAs.

AMS Engineer with 10+ years of experience Available

Posted on February 02, 2018 by Kent Smith

Vinod – AMS Engineer

10+ years of experience in Analog, Mixed Signal and High-speed IO Layout Design of modules and Chip level tasks.
Worked on various technology nodes like 180nm, to 10nm
Proficient in layout design using Cadence Virtuoso XL and Genesys
Custom layout design of blocks, IPs and Full Chip Integration
Floor planning, Power planning and Area estimation of modules
Special planning during placement considering density, HV,EMIR,DRC in deep submicron nodes
Physical Verification of the layout designs

Senior Verification Engineer with 8+ Years Experience Available

Posted on January 31, 2018 by Kent Smith

Sham - Senior Verification Engineer

8yrs+ overall industry experience in Mixed Signal and Digital Verification
Experience in System Verilog and UVM, PSL, and SVA Assertions
Behavioral Modeling of Analog Modules in SV, VAMS, and VHDL
Model Vs. Spice Simulations, Analog Mixed Signal Co-Simulations
Verification of Sound wire, I2C, AHB, and DMA protocols
Functional and Code coverage Analysis

Physical Design & Digital Back-end Engineer Available

Posted on January 29, 2018 by Kent Smith

Jay – Physical Design/Digital Back end Engineer (Available Immediately)

Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule.
Working on complex digital on top lower power design.
Define and verify power intent.
RTL synthesis.
Equivalence check.
Floorplan.
Define power domain and power routing.
Insert power switches.
Isolation and retention cells placement.
CTS and routing.
STA timing analysis.
Worked on top level timing closure.
Bump placement, place bumps with various patterns, assign signals to bumps.
Floorplan, pin placement, RAM placement, power meshes, analog block placement.
Clock tree generation using ccopt.
Worked on timing analysis/closure at both top and block level.
Worked on diversified designs of high utilizations, irregular shapes, and complex clock tree structure with Encounter Foundation Flow.

FPGA Developer & Scripting Expert Available Immediately

Posted on January 26, 2018 by Kent Smith

Ariel – FPGA Developer/Scripting Expert (Available Immediately)

Writes/debugs Python-based firmware test programs for a new device, including battery.
Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
Responsible for the ROM contents on Veridian. Additionally responsible for the new Flash programming and erase routines for the customer. Develops random test bench to exercise the Flash memory.
Wrote a python emulator of the Veridian device. The ARM cortex M0+ core was modelled along with RAM, ROM, FLASH, UART and other blocks. The emulator reads the ELF file containing the binary code compiled by the Keil tools and provides a near clock accurate execution model of that code running on Veridian. This enables the Veridian ROM image to be debugged in advance of Silicon.
Developed a flash emulation on a FPGA. Through a ROM based C program, emulates the Flash API library to allow the Veridian customer to develop their firmware on a FPGA with confidence that it will function on the silicon when it is finished.
Developed a Verilog AMS generator to interface the digital and analog portions of Veridian together. This enabled the design team to simulate concurrently the digital and analog design databases.
Developed a Verilog generator that instantiates the level shifters between the different power domains on Veridian. The Python programs reads an Excel spreadsheet to get a template and then generates a Verilog netlists as per that template.
MSEE, Purdue University, GPA: 5.9/6.0

Design Engineer Experienced in Analog, Mixed Signal & High-Performance RF IC Design

Posted on January 24, 2018 by Kent Smith

Jared – Analog/Mixed Signal Design Engineer

Analog, mixed signal, and high-performance RF IC design.
Switching power converters, LDOs, DC/DC, Buck and Boost, and Power ICs.
Hall sensors for automotive industries.
Analog interface circuits for MRAM, DDR interface.
Ultra-high accuracy CMOS frequency references with mitigated aging.
High-performance RF IC Design and Analog/Mixed Signal IC Design.
State-of-art low-noise and low distortion RF/analog front-ends.
Wireless transceiver system design, video-receivers and mass-storage channels.
IC subsystem design: PLL’s, DDL’s, gain-controls and gm-C filters.
CMOS, BiCMOS and bipolar IC block design such as: LNAs, mixers, phase shifters, amplifiers, comparators, PAs, VCOs, charge pumps, ADCs, DACs, LDOs, power supplies, and bias blocks.

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