Talent 101 Circuit

Barbara – Senior ASIC Physical Design Engineer 

• 20+ years as a physical designer and 10 tape-outs, from netlist to GDS
• 10+ years of methodology development, understanding and using other company’s methodology
• VLSI design work & custom layout using backend tools from Synopsys(ICC1), Cadence(Innovus)
• Large 28 million gate design, physical partition into three blocks. Intel 10nm process and library and IP
• Create and developed a power estimate to create IR/EM correct power rails using Synopsys tools for TSMC flow
• Extensive use of portable scripting languages for tools flow development
• Versed in Microsoft EXCEL spreadsheet for calculations

Charbel – Physical Design Engineer 

• Core experience centered on physical design of large complex CMOS, ASIC, SOC Designs using industry standard tools i.e. Innovus, ICC, talus, and Primetime.
• Responsible for synthesis, formal verification, floor planning (block and top level), power creation and repair, timing driven placement and routing, CTS, timing convergence and analysis, noise convergence and analysis, LVS and DRC.
• Proficient in Cadence's SOC FE, Synopsys' ICC and talus performing synthesis, place and route, timing closure and power analysis.
• Intermediate user of Mentor’s Olympus tool. 
• Proficient user of PTSI from Synopsys and Calibre performing LVS/DRC. 

Harold – Senior Design Verification Engineer

• Design Verification – Constrained Random Full Chip & Unit Level SoC, ASIC, & FPGA
• System Verilog/UVM
• Functional Coverage & Code Coverage
• Assertion (SVA) Based Verification
• Verilog, VHDL
• VCS, IUS, QuestaSim, Verdi
• Python, TCL & PERL Scripting
• VERA/RVM
• Test Bench Architecture & Implementation

Chang – Design Verification Engineer

• High-performance IC/ASIC design and verification.  
• Co-author of two patents.  Strong critical thinking, problem-solving, and planning skills.
• Expert in UVM, System Verilog, VHDL. 
• Experienced in developing and deploying new verification methodologies. 
• Proven track record of developing and delivering high-quality designs on time. 
• Strong leadership and collaboration skills.
• Outstanding team player, mentor, and coach.
• Engineering & Product Management.

Shae – Quality Assurance Test Engineer

• Goal Oriented Quality Assurance Test Engineer with diverse experience in Manual & Automation testing.
• Solid knowledge of software development lifecycle and software testing life cycle.
• Excellent written/oral communication and strong leadership skills. Possess analytical, troubleshooting and problem-solving skills.
• Able to work independently and in a Team environment.
• Worked on Projects with Java Advanced level (Web-based P
  rojects) and on Embedded systems.

Roger – Quality Engineer

• Quality and process engineering knowledge along with positive perspective and effective problem-solving techniques.
• Creates innovative solutions, driving consistent results and improving revenue and growth.
• Inspires the respect and confidence of team members and leaders, while remaining keenly aware of organizational growth initiatives and the company’s potential to meet customer needs.
• Successfully establishes knowledge of Quality Management System and drives for compliance with customer and company requirements, as well as evaluates the risk of new products and processes.
• Develops, executes and documents projects in compliance with committed timelines and project goals.
• Master of Science in Management of Technology.

Jeffrey – Design Verification Engineer

• Extensive experience in the Design Verification in both block and SoC levels 
• Skilled in directed and constrained-random test benches
• Proficient in Object-Oriented programming
• Languages – System Verilog, Verilog, SVA, C, Perl, Shell Scripts, assembly (e200, e500, HC08, HC12)
• Verification methodologies – UVM, VMM
• Simulators – VCS, NC Verilog (incisive), Verilog XL

Maribel – Senior ASIC/SOC Design/Verification Engineer 

• ASIC Firmware/Hardware Integration
• ASIC / SOC Development & Design & Methodology implementation
• Experienced project lead in hard drive controller support.
• ASIC/SOC Conceptual & Layout Design
• Verilog, VDHL, Perl, RTL, UNIX, embedded coding; some OOP C++ and Python.
• Drove/supported clock Generator, SOC Clock Timing, and IDDQ analysis.
• CPU and microarchitectures

Sostenes – FPGA Design Engineer

• 8 Years of strong experience in FPGA/ASIC design and verification flow, Architecture, RTL coding, Functional Verification, Synthesis, Gate level simulations, Static timing analysis (STA), ATPG
• Experience in the design of Xilinx Zynq-7000 Soc, Spartan3E, Lattice LFXP2-40E, and LFXP2-30E & Altera Cyclone III FPGA Boards
• Good Knowledge of ASIC design tools and process flow
• Proficient with C/C++, Verilog HDL, VHDL and System Verilog
• Good knowledge of simulation tools Cadence, Questasim, & Active 

Samantha – Design Verification Engineer  

• Design Verification Engineer with experience in defining testbench architecture, verification planning, and implementation in UVM.
• Knowledge of UVM Environment - Agents (Sequencer, Driver, Monitor), test writing/debug and Coverage.
• Formal Verification, Assertion-based verification.
• Strong knowledge of developing Stimulus, Verification flow, Digital Design, UVM, and OOP.
• Proficient in developing Monitors, Checkers, and Scoreboards in System Verilog.
• Experience on UNIX/LINUX, PERL, Verilog.
• Master of Science in Electrical Engineering