Huang- Physical Design Engineer
- Successful Tapeout multiple ASIC designs, 90nm, 55nm, from RTL handoff to GDS verification
Posted on June 09, 2016 by Kent Smith
Huang- Physical Design Engineer
Posted on March 22, 2016 by Kent Smith
Rajesh - Senior Design Engineer
Posted on February 23, 2016 by Kent Smith
Sri – Analog and Mixed Signal Circuits and Systems Design Engineer
Posted on January 26, 2016 by Kent Smith
Juan - Digital Design and Verification
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