Nick Trompert
Nick Trompert is a Sr. Manager. He is responsible for connecting with the best engineering and information technology talent and resources in the world. He is one of the founders of Talent 101 and joined full time after college.
Sameer – Test Technician
- Load test Programs
- Conduct Testing Eagle, VLCT, LTX, Maverick, impact or other Automated Test Machine
- Qual, Char, Sample and Return testing at Room and Temperature using HTOL
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Zahar – Circuit Design Engineer
- Vast majority of career is in High Performance, Low Power deep sub-micron Digital IC Design
- Strong background in Physical Design and Implementation - can take spec from RTL to GDSII
- Products include Memory, Microprocessor, ASIC and DSP for private industry and government
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Gil – Test Technician
- Load test Programs
- Conduct Testing on ATE (Eagle, Teradyne, LTX, Legacy)
- Manual and Handler testing at Room and Temperature using HTOL
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Ziva – Quality Engineer
- Databases SQL Server, Oracle, Hibernate
- Testing Junit, Selenium, Cobertura, EasyMock, MockObjects
- Identity Management CA IdentityMinder, RedHat Directory Server
- Application Security CA SiteMinder (CA SSO), LDAP
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TJ – Test/Qual Technician
- Conducted hand-screening of prototype IC units on ATE and bench EVM platforms to support customer sample demand.
- Specialized in high-throughput testing of smaller package sizes, including WCSP packages on the order of 1.5 mm dimension.
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Ruben – Analog Design Engineer
- A Digital and Analog Design Engineer with over 10+ years’ experience in hardware and firmware design for control and communications systems. Expertise includes:
- Board-level digital and analog, digital ASIC front end, and FPGA design.
- Embedded microprocessors and DSP applications, buses and interfaces.
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Guadalupe – Physical Design Engineer
- Extensive experience in Transistor Level Circuit Design, ASIC Physical Implementation and Custom Layout Design from high performance Microprocessors to low power high speed ASIC and Mix-signal chip integration.
- Successfully taped out multiple microprocessor and SoC, SRAM IP and standard cell libraries into 16 process nodes. In depth Physical Design experience in dual pattern FinFET technologies including Samsung, TSMC and Intel 20nm, 14nm, 16nm, 10nm, 7nm and 5nm FinFET process.
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Jaycee – Physical Design Engineer
- Core experience centered around physical design of large complex CMOS ASIC SOC designs using industry standard tools i.e. innovus, ICC, talus and PrimeTime.
- Experienced in synthesis, formal verification, floor planning (block and top level), power creation and repair, timing driven placement and routing, CTS, timing convergence and analysis, noise convergence and analysis, LVS and DRC.
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Dalia – Physical Design Engineer
- Experienced Physical Design Engineer in high-technology industry with proven expertise worked on numerous ASIC chip designs using various technology processes and challenging designs in advance CMOS technology nodes.
- Worked on both SOC and CPU designs.
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Manjusha – Digital Design Verification Engineer
- Verification of 2 multi-core (20 processor) complex ASIC SOC designs. Developed Verification plan covering verification strategies - involving module level, inter - module and SOC level functionality tests.
- Performed RTL verification of TI Specific IP’s - PLL controller, Enhanced DMA controller, Interrupt controller, Memory Controllers, VBUS bridges and SCR’s.
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