A Digital and Analog Design Engineer with over 10+ years’ experience in hardware and firmware design for control and communications systems. Expertise includes:
Board-level digital and analog, digital ASIC front end, and FPGA design.
Embedded microprocessors and DSP applications, buses and interfaces.
Extensive experience in Transistor Level Circuit Design, ASIC Physical Implementation and Custom Layout Design from high performance Microprocessors to low power high speed ASIC and Mix-signal chip integration.
Successfully taped out multiple microprocessor and SoC, SRAM IP and standard cell libraries into 16 process nodes. In depth Physical Design experience in dual pattern FinFET technologies including Samsung, TSMC and Intel 20nm, 14nm, 16nm, 10nm, 7nm and 5nm FinFET process.
Core experience centered around physical design of large complex CMOS ASIC SOC designs using industry standard tools i.e. innovus, ICC, talus and PrimeTime.
Experienced in synthesis, formal verification, floor planning (block and top level), power creation and repair, timing driven placement and routing, CTS, timing convergence and analysis, noise convergence and analysis, LVS and DRC.
Experienced Physical Design Engineer in high-technology industry with proven expertise worked on numerous ASIC chip designs using various technology processes and challenging designs in advance CMOS technology nodes.
Verification of 2 multi-core (20 processor) complex ASIC SOC designs. Developed Verification plan covering verification strategies - involving module level, inter - module and SOC level functionality tests.
Performed RTL verification of TI Specific IP’s - PLL controller, Enhanced DMA controller, Interrupt controller, Memory Controllers, VBUS bridges and SCR’s.
