Talent 101 Circuit

Analog IC Power Designer Available

Posted on July 26, 2017 by Kent Smith

Gopi – Analog IC Power Designer (Available immediately)

  • Detailed circuit design including circuit blocks such as Buck/Boost, Charge Pump, ADC etc.
  • Integration of circuit blocks into a top-level design.
  • Detailed simulation including worst case analysis and statistical analysis.
  • Top level simulation and design verification.
  • Guidance to layout and review of layouts for accuracy and optimum performance.
  • Simulation with extracted parasitic elements to verify performance of actual layout.
  • Present results to the TI product team.
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Experienced Analog Design Engineer

Posted on March 06, 2017 by Kent Smith

Joaquin – Analog Design Engineer

  • Excellent Analytical, Problem-solving, Communication and Time-Management skills
  • Proven ability as an effective Multi-tasker and a leader having strong Customer Service skills.
  • Excellent object oriented programming skills and experience in working on UNIX and Linux environments.
  • One-year hands-on experience with Digital Logic Design, Computer Architecture, FSM and Verilog RTL
  • Two years of experience in designing Analog/Mixed Signal and RF Circuits using Cadence Virtuoso
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Design/Verification Engineer with EE Masters Degree Available

Posted on February 15, 2017 by Kent Smith

Sai - Analog Mixed Signal Design/Verification Engineer

  • Design of Analog blocks for capacitive touch circuits.
  • Analog-Mixed signal verification at chip level.
  • Write, debug, and run test benches using Verilog-A/Verilog-AMS/System Verilog to verify both models and transistor-level circuits at all operating modes using the AMS-Designer environment.
  • Design functional models for Buck, Boost, LDO, Load Switch, RCO, Rectifiers, Analog comparators, PLL, ADCs in Verilog-AMS/DMS.
  • Integration of full chip and Top Level simulations for ICs with the Power Management and Wireless Battery Charging circuits.
  • Create, debug, and run test benches to execute transistor-level performance verification over design corners using the Spectre circuit simulator.
  • Mix and match of Verilog and Spice netlist in Chip Level Simulations.
  • Master of Science – Electrical Engineering
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Analog IC Layout Design Engineer Available

Posted on December 27, 2016 by Kent Smith

Vincent – Analog IC Layout Design Engineer  

  • Precision oscillator & test circuits for Battery Management IC.
  • Design of 14 bit column ADC for CMOS night vision IC.
  • Design & characterization of blocks for mixed signal & power management ICs.
  • Design & characterization of Buck-boost voltage regulator.
  • Design & characterization of Servo motor controller IC’s for hard disk drive applications.
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Electronics Engineer Experienced in Analog + Digital Circuit Design

Posted on December 19, 2016 by Kent Smith

Clay – Electronics Engineer  

  • Electrical Engineering with 6+ years of engineering experience  
  • Analog and Digital Circuit Design
  • Schematic Capture (Altium, EAGLE, PSpice)
  • PCB Layout (Altium, EAGLE)
  • Prototyping, Testing and PCB modification
  • Embedded Scripting using C++ and BASH
  • Proficient with Lab Testing Equipment (Oscilloscopes, Logic Analyzers, etc.)
  • IC Design and VLSI Layout (MEDICI, TSUPREM-4, Electric 8.10)
  • MATLAB programming and graphics
  • Digital Design using VHDL
  • Familiar with UNIX and Linux operating systems
  • Proficient with all applications in the Microsoft Office Suite, including Visio
  • Master of Science in Electrical Engineering
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Mixed Signal Design Engineer Available

Posted on December 07, 2016 by Kent Smith

Juan – Mixed Signal Design Engineer  

  • Extensive experience in Complex Analog and Mixed-signal circuit design & characterization.
  • Great experience in RFIC circuits, matching and components in Transceiver.
  • Thorough understanding in latest Process and Technology including FinFET.
  • Strong experience in Mixed-Signal Verification/validation/SI and Integration.
  • Working experience in Voltage Regulation, LDOs, Bandgaps, and Power Supply.
  • Outstanding record in building new team, capability, and business.
  • Efficient in developing CAD/PDK/FDK flows with Industry leading Cadence, Synopsys, and Mentor Graphics tools.
  • Master of Engineering in Electrical Engineering.
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High-Precision Analog Design Engineer Available

Posted on November 21, 2016 by Kent Smith

Dason – Analog Design Engineer

  • Cadence Virtuoso
  • DRC/LVS verification using Calibre
  • Assura, and PVS
  • High precision analog design techniques such as cross-coupling and interdigitation
  • Experienced with high-voltage (>40v) processes with multiple isolation schemes on shallow and deep-epi substrates
  • Experienced with the physical implementation of a variety of power management and signal chain IC's
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Analog IC Design Engineer Available

Posted on November 07, 2016 by Kent Smith

Chang – Analog IC Design Engineer

  • Redesigned LFO circuit for battery management IC BQ796 to reduce power & supply voltage & eliminate resistor trimming.
  • Simulated LFO across corners & uniform distribution (Latin Hypercube) with cadence spectre MIDAS & ADEXL & FARM. Uniform distribution required several design changes to hit effective 6 sigma performance.
  • Oversaw relay out of LFO.
  • Designed new TMODE circuit for IC BQ796.
  • Simulated TMODE with spectre ADEXL & FARM.
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Senior Analog Layout Engineer Experienced in Multiple Circuit Types

Posted on September 21, 2016 by Kent Smith

Larry – Senior Analog Layout Engineer

  • Analog design experience in OpAmps, comparators, LDO’s, regulators, bandgaps, DAC, ADC, PLL’s, VCM’s and many other circuit types.
  • These projects vary from block level to top chip thru tapeout.
  • Layouts designed to perform to specifications documentation.
  • Experience with LBC7, LBC8, LBC9 and more.
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Senior Analog Layout Engineer Available

Posted on September 19, 2016 by Kent Smith

Dwayne – Senior Analog Layout Engineer  

  • Senior Mask Designer with Top Level Floor Planning.
  • Extensive layout experience in both Analog and Logic Circuits including ESD, I/O’s, Standard Cells, Self-Bias PLL’s, LC Tank PLL’s (8 Ghz), DLL’s, Precision OpAmps, Low Noise Amps, Comparators (including hysteresis & latched output types), Commutating Amps, LDO’s (including Low Pwr), Hard Macro’s (Analog sub-system blks), Test Chip top level create (including schematic, layout, and I/O Ring) and full Mixed Signal Chips.
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