Talent 101 Circuit

Luis – Mechanical Engineering

• Experience in equipment design, analysis, project management, manufacturing, testing, assemblies and installation. Expert in using Finite Element Analysis (FEA), Computational Fluid Dynamics (CFD) and engineering calculation (using MathCAD). Experienced in equipment specification, datasheet, setup, 2D drawing, 3D model, P & ID, HAZOP/HAZID, maintenance and handling check, functional verification and package engineering. Visited sites for prototype test, hydro test, pressure test, factory acceptance test (FAT) and system integration test (SIT).  Visited sites domestic and international for project management and engineering issues.
• Product Design & Analysis - Used Design for Manufacturability (DFM), Design for Assembly (DFA), FEA, welding, metallurgy, GD&T (ASME Y14.5), 2D, 3D, BOM for robust design and integrity.

Nathan – FPGA Developer/Scripting Expert Available July 1, 2017

• Writes/debugs Python based firmware test programs for a new device, including battery.
• Implements both C and Python elliptical curve cryptographic routines and test bench for digital signatures to validate battery packs.
• Responsible for the ROM contents on Veridian. Additionally responsible for the new Flash programming and erase routines for the customer.  Develops random test bench to exercise the Flash memory.
• Wrote a Python emulator of the Veridian device.  The ARM cortex M0+ core was modelled along with RAM, ROM, FLASH, UART and other blocks.  The emulator reads the ELF file containing the binary code compiled by the Keil tools and provides a near clock accurate execution model of thatcode running on Veridian.  This enables the Veridian ROM image to be debugged in advance of Silicon.
• Developed a flash emulation on a FPGA. Through a ROM based C program, emulates the Flash
• API library to allow the Veridian customer to develop their firmware on a FPGA with confidence that it will function on the silicon when it is finished.
• Developed a Verilog AMS generator to interface the digital and analog portions of Veridian together. This enabled the design team to simulate concurrently the digital and analog design databases.
• Developed a Verilog generator that instantiates the level shifters between the different power domains on Veridian. The Python programs reads a Excel spreadsheet to get a template and then generates a Verilog netlists as per that template.

Nikko – Electrical Engineer

• Electrical Engineer with over 10 years of embedded microcontroller/FPGA software/firmware experience
• Verilog/VHDL design, development, debug/troubleshoot, test and deploy experience
• VxWorks (App Level), LabVIEW (App level), and Proprietary RTOS based multi-tasking, multi-processor software and Altera /Xilinx Verilog/VHDL Signal Tap/Chip Scope Pro Simulation and Control FPGA hardware.
• Expertise includes technical design, development, debug/trouble-shoot, test and deployment of compact microcontroller/FPGA based systems designed to control solid-state recorders
• Bachelor of Science in Electrical Engineering

Thie – System Engineer    

• Experience as a System Engineer with excellent critical thinking and programming skills
• Programming/Scripting/Debugging: C/C++ (Object Oriented), bash, csh, Tcl, PERL, Python, GNU debugger
• Hardware Description Languages: VHDL, Verilog, System Verilog. UVM basics

Jerry – Physical Design Engineer  

• Design Tools : Cadence - Virtuoso, Encounter, Assura (DRC, LVS), Spectre, Tempus, Conformal(LEC), Mentor Graphics' Calibre – DRC, LVS, PEX, RVE, Micromagic – SUE (Schematic) & MAX (Layout) Synopsys-  Design Vision, Primetime, TetraMAX, ModelSim, Xilinx – ISE  
• Programming : Verilog, Perl, C, C++ HSPICE

Louie – System Engineer    

• Programming Language:  C, C++, and C #, Java, Python, RTL, VHDL, Verilog, and System Verilog, Assembly language
• EDA Tools:  Cadence (Virtuoso, Encounter), Hspice, Synopsys (Design Compiler), Mentor Graphics (ModelSim), Prime Time, EDA playground
• Tools/Applications:  MATLAB, Flex and Bison, Visual Studio, Dev C++ (IDE), Code Block, Eclipse

Dipta – Electrical Engineer

• Worked on developing a DC-DC boost converter to be used for consumer electronics using IBM 0.18um technology
• Studied and redesigned different DC-DC boost topologies to achieve maximize voltage efficiency
• Assisted Ph.D. candidates and other graduate students with PCB layout design for their research projects
• Aided Ph.D. candidates with designing components of PLL (phase locked loop) like VCO (voltage controlled oscillator) and filters
• IC Design Tools:  Cadence Virtuoso, Synopsys DC, Cadence Assura (DRC, LVS,QRC), Cadence Encounter, OrCAD, Altera Quartus II, Multisim, Altium Circuit Maker, LabVIEW

Samuel – Senior IC Layout Engineer

• Solid history of establishing and maintaining positive working relationships with Design, Product and Test Engineers
• Analytical and resourceful in solving new and challenging problems
• Self-motivated individual contributor and positive team player  
• Goal-directed with focus on details and follow-through
• Cadence Virtuoso and VXL
• Hercules (DRC, LVS, EMC)

Gilberto – Electrical Engineer  

• Electrical Engineer with total 5+ years of engineering experience
• Excellent knowledge of digital and analog system design and testing
• Extensive knowledge of the design concepts and applications of signal processors, ASIC Design & Verification, Microprocessors and very-large-scale integration circuit systems

Jun – IC Layout Engineer

• Hands on experience with FPGA Design and Implementation, RTL Design and Verification, ASIC Design.
• Hands on experience with Nexys 2 Spartan-3E FPGA Trainer Board and Mercury Development Board.
• Excellent independent work on ASIC/ PD flow and hands on experience with RTL to GDS II flow.
• Hands on experience with Floorplan, Power plan, Place & Route, CTS, STA and Timing Closure.