Talent 101 Circuit

Jose – IC Design Engineer

• Oversaw development of all power management IP (Buck, Boost, LDOs) and other analog IP (GPADC, PLL)
• Oversaw Floor-planning and module layout development
• Managed customer interaction to make sure alignment was maintained on technical and project aspects
• Designed boot regulator to allow switch to be brought above input voltage to improve RdsOn

Sai - Analog Mixed Signal Design/Verification Engineer

• Design of Analog blocks for capacitive touch circuits.
• Analog-Mixed signal verification at chip level.
• Write, debug, and run test benches using Verilog-A/Verilog-AMS/System Verilog to verify both models and transistor-level circuits at all operating modes using the AMS-Designer environment.
• Design functional models for Buck, Boost, LDO, Load Switch, RCO, Rectifiers, Analog comparators, PLL, ADCs in Verilog-AMS/DMS.
• Integration of full chip and Top Level simulations for ICs with the Power Management and Wireless Battery Charging circuits.
• Create, debug, and run test benches to execute transistor-level performance verification over design corners using the Spectre circuit simulator.
• Mix and match of Verilog and Spice netlist in Chip Level Simulations.
• Master of Science – Electrical Engineering

Kent– Circuit System/Design Engineer  

• Power over Ethernet (PoE)
• Power over Data Lines (PoDL) integrated circuits
• Current-limited voltage source for PoDL detect circuit
• Sense chopper amplifier for PoE
• Design for satellite TV receiver set top box SOC

Kumar – Layout Engineer

• Desigining custom TCell’s for layout using C language in various semiconductor process nodes ranging from 0.18um – 45nm.
• Layout of new memory IP’s in various semiconductor process using L-edit.
• Managing the layouts of existing memory IP’s and performing physical verification using Calibre.

Maha - Electrical Engineer

• VLSI design
• Advanced Digital LogicM
• Testing and Testable design of VLSI
• Computer architecture
• Analog IC design
• RF and Microwave Amplifier design
• Digital Signal Processing
• Master of Science – Electrical Engineering

•  Experience in CMOS analog circuit desiger
• Strong in-depth knowledge in digital logic design of Verilog and HDL, Modelsim and Xilinx IS tool
• Knowledge of complex AC/DC analysis (poles, zeros, compensation)
• Full Custom Mixed Signal / Custom Layout and using DRC, LVS for verification
• Experience in Assembly Language, C++, Verilog, Perl, Matlab. HSPICE, Cadence, Mentor Graphic
• Experience using Verilog, Modelsim & Xilinx ISE tools such as Programmable Processors; Finite
• State Machine; Control unit with PC, IR, & controller; Memory Control and Ring Oscillators.
• MS in Computer Engineering

Kishore – Digital Designer

• Talented semiconductor engineer with extensive experience in the high-tech industry
• ASIC Physical Design
• Front-End Development  
• Flow Implementation  
• SoC Integration
• Design Verification
• Machine Learning
• Product Management
• B.S. in Computer Engineering

Thomas – Mechanical Designer

• Certified SolidWorks/Professional
• Design for manufacturability
• PDM
• GD & T
• Rapid Prototyping/3D Printing
• Sheet Metal
• Large Assembly Design (1000+ parts)
• Surface Modeling
• Machining
• Hydraulic/pneumatic systems
• 3D rendering/animation
• SolidWorks/3D Via Composer/AutoCAD
• AAS - Drafting & Design Technologies

Maria– Senior Layout Engineer  

• Senior IC Layout Designer/Leader with strong people, team-building, and project management skills.
• Lead Layout Designer, for new Rad Hard Microwave 10GHZ designs.
• Utilizing SiGe IBM,HP for RF circuitry (TX, RX), etc.
• Created various IP in 45nm blocks.
• Trained on the new 10nm FinFET process.
• Performed layout on various FinFET Macros.
• Utilizing bicmos 8HP- 90nm, and cms 9flp-130nm for RF Circuitry.
• Currently kicking off new 14nm FinFET IBM projects for various new designs.

Rene – Circuit Design/Layout Engineer

• CMOS Digital 16x16 crossbar switch - Tools: Cadence Virtuoso.
• Designed a digital switch using 16:1 multiplexer and 64-bit shift register on IBM 180 nm CMOS technology.
• Performed DRC, LVS and parasitic extraction along with post-layout simulation for the PCB layout of the circuit.
• Achieved an overall speed of 22.93 GHz for the entire circuit.
• Datapath synchronous controller design - Tools: Altera Quartus II.
• Designed an ASIC using a datapath and controller to perform the Newton-Raphson equation to calculate inverse of a number.
• Modeled the controller using only Verilog and used schematic capture and Verilog for the datapath.
• Worked on block level synthesis, circuit debugging and static timing analysis on the entire design.
• CMOS DC-DC boost converter - Tools: Cadence Virtuoso.
• Designed and simulated a DC-DC converter using boost topology which increases a low input dc voltage to a high dc voltage.
• Utilized the analog design environment on Cadence to run transient and dc simulations on multiple nodes of the circuit.
• Obtained a dc output of 1.5 V for a dc input of 0.8 V using TSMC 130 nm CMOS technology.
• Master of Science in Electrical Engineering.