Talent 101 Circuit

Manchu – Validation Engineer

• Experienced developing tests on various ATE (Automated Test Equipment) for Semiconductor IC’s (Integrated Circuits)
• Performed analysis on design/production data, using 6 sigma, to determine the production worthiness of the test program(s)
• Implemented methods and procedures for testing the precision, and accuracy, of products

Sydney - Electrical Engineer   

• ASIC design experience in taking designs from the preliminary netlist step through tape out.
• ASIC/FPGA development skills including: logic simulation, formal verification, static timing analysis, floor planning, place and route, timing closure, test vector generation, power analysis, signal integrity checks, LVS/DRC checks, limited logic synthesis and overall EDA methodology/flow compatibility issues.

Jian – IC Layout Engineer

• Good understanding of CMOS Design, circuit simulation, circuit board and basic gates like NAND, MUXs,FFs etc.
• Familiar with IPC-A-600,610,613 standards
• Strong hold on IC Fabrication processes like diffusion, oxidation, lithography, etching, PVD and CVD
• Excellent team player with good communication, presentation and organization skills
• VLSI:  CMOS Logic, Circuit simulation, Semiconductor Fabrication Processes, Layout design rules,Verilog/VHDL programming, Cadence Tool, RTL design flow, Combinational and Sequential circuit design.

Rafa – Mechanical Engineer

• 2D/3D CAD(AutoCAD, Solidworks and ProE)
• Finite Element Analysis (ANSYS)
• Manufacturing
• Sheet Metal Design
• Geometric Dimensioning and Tolerance (GD&T)

George - Electrical Engineer  

Joaquin – Analog Design Engineer

• Excellent Analytical, Problem-solving, Communication and Time-Management skills
• Proven ability as an effective Multi-tasker and a leader having strong Customer Service skills.
• Excellent object oriented programming skills and experience in working on UNIX and Linux environments.
• One-year hands-on experience with Digital Logic Design, Computer Architecture, FSM and Verilog RTL
• Two years of experience in designing Analog/Mixed Signal and RF Circuits using Cadence Virtuoso

Adam – Senior Layout Designer

• Experienced in digital layout in areas such as microprocessor, Digital Signal Processor (DSP), System on a Chip (SoC), RAM, EPROM, and fully differential logic
• Experienced in analog layout in areas such as Comparators, Digital to Analog Converters (DAC), Phase Lock Loops (PLL), Bandgaps, and Voltage Regulators

Naveen - Analog Layout Engineer  

Base Band Filter (BBF): 

• Description: It amplifies difference of voltage.
• Targeted Technology: TSMC 90nm
• Role: Develop layout from schematic, floor plan, placement, routing and clean DRC, LVS and QRC.
  

Low Noise Amplifier (LNA):

• Description: LNA is an electronic amplifier that amplifies a very low-power signal without significantly degrading its signal-to-noise ratio.
• Targeted Technology: TSMC 90nm
• Role: Develop layout from schematic, floor plan, placement, routing and clean DRC, LVS and QRC.

Changpu – Characterization Engineer

• Developed and completed the following items for DC/DC Buck converter characterization and verification:
• Characterization Plan
• Used Cadence Capture/Allegro to Design the Schematic and Layout for Evaluation board
• Bench Hardware Setup
• LabVIEW GUI
• Failure Analysis on the Hardware

John - Analog IC Designer  

• Designed the following blocks:
• FLL frequency control loop for  buck converter
• Rail to Rail PWM comparator
• Band Gap reference
• Compensator