Talent CIRCUIT (39)

ASIC/FPGA Design & Verification Engineer Available

Posted on December 21, 2016 by Kent Smith

Ameen – ASIC/FPGA Design & Verification Engineer

Experience in ASIC/FPGA Design and Verification, Computer Architecture, Synthesis, RTL Debug, Python, C.
Strong knowledge of creating Test Bench, Static Timing Analysis, ASIC Design flow, CMOS Logic Design.
Understanding of Caches Coherence Protocol (MESI), SoC Integration, Semiconductor Device, and Physics.
Knowledge of DFT implementation and Scan insertion, ATPG, Logic BIST.
Good team player with excellent communication skills.
Languages: Verilog HDL, System Verilog, UVM, C, C++, Java, Data Structures, Perl, Python.
EDA Tools: Quartus II, MODELSIM, Synopsys Design Compiler Libero IDE, Oscilloscope, Logic Analyzer, Cadence Virtuoso, Cadence Encounter, NC Verilog, I Verilog, Synopsys VCS (Verilog Compiler Simulator), GTKWave, Synopsys Design Vision, Synplify Pro, UNIX Working Environment.
M.S. in Electrical Engineering.

Electronics Engineer Experienced in Analog + Digital Circuit Design

Posted on December 19, 2016 by Kent Smith

Clay – Electronics Engineer

Electrical Engineering with 6+ years of engineering experience
Analog and Digital Circuit Design
Schematic Capture (Altium, EAGLE, PSpice)
PCB Layout (Altium, EAGLE)
Prototyping, Testing and PCB modification
Embedded Scripting using C++ and BASH
Proficient with Lab Testing Equipment (Oscilloscopes, Logic Analyzers, etc.)
IC Design and VLSI Layout (MEDICI, TSUPREM-4, Electric 8.10)
MATLAB programming and graphics
Digital Design using VHDL
Familiar with UNIX and Linux operating systems
Proficient with all applications in the Microsoft Office Suite, including Visio
Master of Science in Electrical Engineering

Embedded Systems Engineer Available

Posted on December 15, 2016 by Kent Smith

Blasios – Embedded Systems Engineer

Deep knowledge of electronics, computer hardware, and software.
Good understanding of OS kernel internals especially Linux and UNIX.
Admirable experience as an Engineer in embedded systems test environment.
Familiarity with Assembly Language, C/C++, Microprocessors, Microcontrollers, and RTOS's.
Proven firmware design and development skills with a deep understanding of embedded systems, microprocessors (Microchip, Coldfire527X, Powerpc860), interconnection bus protocols (I2C, SPI, CAN,RS232, RS485, etc.)
Strong testing and problem-solving skills with ability to use varieties of testing tools such as logic analyzers, oscilloscopes, Multi-meters, signal generator, spectrum analyzer.
Masters in Engineering in Aerospace.

Senior Layout Design Engineer Available

Posted on December 13, 2016 by Kent Smith

Vanu – Senior Layout Designer Engineer

Proficient with SiGe process as IBM bicmos 8hp, 9hp. TOWER-JAZZ bicmos Ha, H3, and TSMC process as 16 nano, 20 nano, 40, 60, 90 etc.
Perform layout of high-speed VGA, TIA, LDO, OpAmp, Bias, Clamp, ADC, DAC, Power Generation, RF amplifiers, Detectors, Filters, Oscillators, etc.
Module generated, synchronized clone with virtuoso up to date Cadence v6.16.
High performance layout Electro migration, IR drop, ESD, Latchup.
Ability to layout analog circuitry in a size/time constrained environment.

Mixed Signal Design Engineer Available

Posted on December 07, 2016 by Kent Smith

Juan – Mixed Signal Design Engineer

Extensive experience in Complex Analog and Mixed-signal circuit design & characterization.
Great experience in RFIC circuits, matching and components in Transceiver.
Thorough understanding in latest Process and Technology including FinFET.
Strong experience in Mixed-Signal Verification/validation/SI and Integration.
Working experience in Voltage Regulation, LDOs, Bandgaps, and Power Supply.
Outstanding record in building new team, capability, and business.
Efficient in developing CAD/PDK/FDK flows with Industry leading Cadence, Synopsys, and Mentor Graphics tools.
Master of Engineering in Electrical Engineering.

IC Layout Design Engineer Available

Posted on December 05, 2016 by Kent Smith

Mason – IC Layout Design Engineer

Designed various circuit blocks with Dongbu HiTek CMOS 0.18 um Design Rules.
Built custom made standard cells (INV, NAND).
Driver cells that drove output PMOS and NMOS for a buck regulator.
These standard and driver cells were used towards OLED driver for cell phone displays.
Layout tools: Cadence Virtuoso XL Editor (VXL), Cadence Virtuoso Schematic Composer, PCELL utility, Calibre DRC/LVS.

Analog Mixed Signal (AMS) Verification Engineer Available

Posted on December 02, 2016 by Kent Smith

Sajeel- Analog Mixed Signal (AMS) Verification Engineer

Digital and AMS verification of Battery management, Battery Charger, Power resources (LDO’s, DCDC’s, REFERENCE), ADC’s, Fuel Gauge, PMIC’s, storage devices, automotive devices.
Experience of Mixed Signal Verification of PMIC’s, storage devices.
SoC verification(C / Specman based), RTL, GATE Level at TOP Level.
Behavioral models development for the Analog blocks using VHDL.
Top Level mixed mode simulations for verifying Digital and Analog integration and analog block functionalities.

Experienced Lead Senior System Engineer Available

Posted on November 30, 2016 by Kent Smith

Manuel – Lead Senior System Engineer

Deep understanding of analog matching requirements, common centroid techniques for minimizing V offsets in matched pairs and other circuits; ensuring high yield processing and circuit performance through the use of identical processing environments/device orientations, dummies, WPE compliant enclosures, etc.; capacitive coupling minimization through the use of spacing and/or co-ax shielding on critical AC signals.

Experienced Full Stack Developer Available

Posted on November 28, 2016 by Kent Smith

Lemmy – Full Stack Developer

Extensive experience in Design and Development of Distributed and Client-Server Enterprise applications using Object Oriented Analysis, Design and JAVA, J2EE Technologies.
Proficient in wide array of Java/J2EE technologies such as JSP/Servlets, Struts/Spring/Hibernate frameworks. Web Services using SOAP, XML, EJB, JSON and JDBC.
Comfortable in configuration and deployment of multi-tier applications using servers like Weblogic, Tomcat, and JBOSS.

High-Precision Analog Design Engineer Available

Posted on November 21, 2016 by Kent Smith

Dason – Analog Design Engineer

Cadence Virtuoso
DRC/LVS verification using Calibre
Assura, and PVS
High precision analog design techniques such as cross-coupling and interdigitation
Experienced with high-voltage (>40v) processes with multiple isolation schemes on shallow and deep-epi substrates
Experienced with the physical implementation of a variety of power management and signal chain IC's

Talent 101 Circuit