Talent 101 Circuit

Ramesh - Senior VLSI Design Engineer

• Five years of experience as Physical Layer IP Team lead, contributed mainly as Lead Designer.
• Contributed to multiple activities from Pre-sales to Silicon bring up of PHY IPs.
• Eleven years of Career in semiconductor field covering Design, Synthesis, STA, FPGA, DFT.
• Excellent in defining timing constraints including tight Analog to Digital interface signals.
• Performed STA for 6 Projects.
• Good combination of strong design skills with in depth timing visualization.
• Verilog RTL designer with experience in Multi Clock Domain Designs.
• Expertise in SOC level and IP level DFT Design, Verification and Silicon testing including DC and at speed scan, Memory BIST.
• Closely works with STA / PnR team to address challenging timing / area closures, ECOs.
• Performed design evaluation in Xilinx FPGAs.

Vinod – AMS Engineer

• 10+ years of experience in Analog, Mixed Signal and High-speed IO Layout Design of modules and Chip level tasks.
• Worked on various technology nodes like 180nm, to 10nm
• Proficient in layout design using Cadence Virtuoso XL and Genesys
• Custom layout design of blocks, IPs and Full Chip Integration
• Floor planning, Power planning and Area estimation of modules
• Special planning during placement considering density, HV,EMIR,DRC in deep submicron nodes
• Physical Verification of the layout designs

Jay – Physical Design/Digital Back end Engineer (Available Immediately)

• Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule.
• Working on complex digital on top lower power design.
• Define and verify power intent.
• RTL synthesis.
• Equivalence check.
• Floorplan.
• Define power domain and power routing.
• Insert power switches.
• Isolation and retention cells placement.
• CTS and routing.
• STA timing analysis.
• Worked on top level timing closure.
• Bump placement, place bumps with various patterns, assign signals to bumps.
• Floorplan, pin placement, RAM placement, power meshes, analog block placement.
• Clock tree generation using ccopt.
• Worked on timing analysis/closure at both top and block level.
• Worked on diversified designs of high utilizations, irregular shapes, and complex clock tree structure with Encounter Foundation Flow.

Jared – Analog/Mixed Signal Design Engineer

• Analog, mixed signal, and high-performance RF IC design.
• Switching power converters, LDOs, DC/DC, Buck and Boost, and Power ICs.
• Hall sensors for automotive industries.
• Analog interface circuits for MRAM, DDR interface.
• Ultra-high accuracy CMOS frequency references with mitigated aging.
• High-performance RF IC Design and Analog/Mixed Signal IC Design.
• State-of-art low-noise and low distortion RF/analog front-ends.
• Wireless transceiver system design, video-receivers and mass-storage channels.
• IC subsystem design: PLL’s, DDL’s, gain-controls and gm-C filters.
• CMOS, BiCMOS and bipolar IC block design such as: LNAs, mixers, phase shifters, amplifiers, comparators, PAs, VCOs, charge pumps, ADCs, DACs, LDOs, power supplies, and bias blocks.

Kevin– Analog/Mixed Signal Design Engineer

• Buck, Boost, LDO, Regulators ADC
• 1.2V buck converter, 50mA output
• 3.3V boost converter, 150mA output
• Current-limited voltage source for PoDL detect circuit.
• Sense chopper amplifier for PoE.
• Audio codec Development

Julian - Physical Design Engineer

• More than 10 years as a Physical Design Engineer to tape out various products from SOC like Ethernet, Serdes, to RF/Mixed Signal chips like Bluetooth, NFC, touch screens, AD/Da etc.

• Taped out with various processes like 28nm, 45nm, 65nm, 90nm, 130nm, 180nm and foundries like TSMC, UMC, IBM, Charter, X-FAB, Jazz Semiconductors etc.

• More than 10 years as physical design CAD for the flow development, support and trains

• A track record of Project Leadership on large SOC implementations like 48 million gate Serdes switcher to small project like touch screen sensor
  

Norma – Physical Design Engineer

• Performed RTL Synthesis, Physical implementation through floor planning, auto place and route, clock tree synthesis and static timing analysis at 22nm

• Developed automated scripts using TCL, Perl with EDA tools to fix different violations like maxcap, maxtran, hold, setup and DRC
• Improved test coverage results by 25% by developing testability flow for three EDA tools and managed eight design automation tools
• Worked closely with tool vendors for technology specific feature enhancements for advanced Intel node process
• Documented tool usage procedures, prepared training documents and presented information to customers
• Managed and executed assigned design section of a micro server chip project using Synopsys tools
  

Akron - Analog IC Design Engineer

• RF/Analog-Mixed Signal IC Design, Layout Design, Verification and Testing
• Experienced in CMOS Circuit Design, ASIC Design and Custom Layout.
• Experience with industry standard Cadence, Spectre RF, AWR MWO, Eagle CAD PCB design tool
• Designing Operational Amplifiers, VGAs, ADCs, DACs, Bandgap references, RF Circuits, LNAs, Mixers, VCOs, PLLs
  

Chad – Analog IC Power Engineer

• Switching Power Converters, LDOs, DC/DC, Buck and Boost and Power ICs
• Hall sensors for automotive industries.
• Analog interface circuits for MRAM, DDR interface
• Ultra-high accuracy CMOS frequency references with mitigated aging
  

Tiffany – Hardware Design Engineer

• Highly competent, smart-working and motivated detailed Hardware Designer and PCB Designer with exemplary work ethics. 
• Expert at applying technical know-how to integrate and operate IT hardware, software and application solutions. 
• Remarkable experience with Layout, fabrication and assembly of Multilayer PCBs 
  Sound knowledge of PADS Power PCB and OrCAD Schematic Capture 
• Layout complex high-speed boards for current and next generation product lines.