Talent 101 Circuit

Phallon – Digital Design Engineer

• ASIC and FPGA device experience

Fang – Physical Design/Digital Back end Engineer 

Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule

• Working on complex digital on top lower power design
• Define and verify power intent
• RTL synthesis
• Equivalence check
• Floorplan
• Define power domain and power routing

Mickey – Analog IC Power Engineer

• Detailed circuit design including circuit blocks such as Buck/Boost, Charge Pump, ADC etc.
• Integration of circuit blocks into a top-level design.
• Detailed simulation including worst case analysis and statistical analysis.
• Top level simulation and design verification.

Kane – Physical Design Engineer  

• Physical Design
• Block level Implementation and physical design of various blocks for 7nm processor.
• Synthesis, place and route, timing, clock tree synthesis, scan chain.  IR and EM study and fixes.  DRC, LVS clean up
• Execution Unit
• Fetch Unit
• Memory Subsystem

Fang – Physical Design/Digital Back end Engineer (available July 1, 2017)

Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule

Sangh – Physical Design/Digital Back-end Engineer (available July 1, 2017)

Part of physical design team, worked closely with digital and analog teams to deliver design of mixed signal block on time under tight schedule

• Working on complex digital on top lower power design
• Define and verify power intent
• RTL synthesis
• Equivalence check
• Floorplan
• Define power domain and power routing

Jerry – Physical Design Engineer  

• Design Tools : Cadence - Virtuoso, Encounter, Assura (DRC, LVS), Spectre, Tempus, Conformal(LEC), Mentor Graphics' Calibre – DRC, LVS, PEX, RVE, Micromagic – SUE (Schematic) & MAX (Layout) Synopsys-  Design Vision, Primetime, TetraMAX, ModelSim, Xilinx – ISE  
• Programming : Verilog, Perl, C, C++ HSPICE

Wang – Design/Layout Engineer  

• Design/Layout Engineer with over 10 years’ experience dealing with the design/layout of analog and/or mixed signal products
• Design lead of Serial EEPROM (SPI/I2C) products which include analog (voltage/current references), and +16V (charge-pumps, regulators, level-shifting) circuit blocks
• Design lead of RTCC products (SPI/I2C) which include analog (voltage/current references), memory (EEPROM, SRAM), and +16V (charge-pumps, regulators, level-shifting) circuit blocks

Jared – Component Design Engineer

• Electrical Efficiency
• Control Systems.
• Power Electronics
• Bioelectronics
• Voltage Regulators
• Power Systems
• Python Development

Juan – IC Design Engineer   

• Creative and competent IC design engineer capable of working as an individual contributor or working effectively within a team environment in the technical definition, design and validation of schedule driven mixed signal IP
• Extensive experience in the design, implementation and debug of ESD and latch-up tolerant networks and circuits
• Highly proficient in floor-planning of circuits, ESD/latch-up tolerant layout practices and analog layout techniques