Talent 101 Circuit

Jose – IC Design Engineer

• Oversaw development of all power management IP (Buck, Boost, LDOs) and other analog IP (GPADC, PLL)
• Oversaw Floor-planning and module layout development
• Managed customer interaction to make sure alignment was maintained on technical and project aspects
• Designed boot regulator to allow switch to be brought above input voltage to improve RdsOn

Kent– Circuit System/Design Engineer  

• Power over Ethernet (PoE)
• Power over Data Lines (PoDL) integrated circuits
• Current-limited voltage source for PoDL detect circuit
• Sense chopper amplifier for PoE
• Design for satellite TV receiver set top box SOC

Thomas – Mechanical Designer

• Certified SolidWorks/Professional
• Design for manufacturability
• PDM
• GD & T
• Rapid Prototyping/3D Printing
• Sheet Metal
• Large Assembly Design (1000+ parts)
• Surface Modeling
• Machining
• Hydraulic/pneumatic systems
• 3D rendering/animation
• SolidWorks/3D Via Composer/AutoCAD
• AAS - Drafting & Design Technologies

Jake – PCB Layout Designer

• Mentor Expedition
• Mentor Design Capture
• Mentor DX Designer
• Cadence Allegro
• Cadence HDL
• OrCAD/Cadence Design Entry CIS
• Altium
• Pads
• Seica Viva
• AAS Electronics Engineering Technologies

Demarco – Mechanical Designer & Manufacturing Engineer

• 10 + years experience as a Mechanical Designer & Manufacturing Engineer.
• Strong technical skills in product development and manufacturing support, in various production environments.
• Design experience includes die-cast, plastic (injection molded, casted, and extruded), forgings, sheet metal, and machined parts.
• Diverse computer skills that include SolidWorks and Microsoft Office.
• Experience developing and maintaining mechanical/electrical SPP components.
• Technical review and editing of SolidWorks models and drawings of components used in complex medical device assemblies.
• Supported Document and Quality Control activities.
• Freelance product and tooling design (SolidWorks/DraftSight).
• Created part and assembly product drawings using SolidWorks.
• Master of Science in Engineering Technology.

Andres – Senior IC Layout Designer  

• Cadence Virtuoso and VXL
• Hercules (DRC, LVS, EMC)
• Calibre (DRC, LVS)
• Custom Analog Layout
• Mentor Tools Suite
• Pulsic Unity (Routing tool)
• CMOS Digital Layout
• Mixed Signal Layout
• Bachelor of Science in Chemistry & Microbiology

Vincent – Analog IC Layout Design Engineer  

• Precision oscillator & test circuits for Battery Management IC.
• Design of 14 bit column ADC for CMOS night vision IC.
• Design & characterization of blocks for mixed signal & power management ICs.
• Design & characterization of Buck-boost voltage regulator.
• Design & characterization of Servo motor controller IC’s for hard disk drive applications.

Ameen – ASIC/FPGA Design & Verification Engineer

• Experience in ASIC/FPGA Design and Verification, Computer Architecture, Synthesis, RTL Debug, Python, C.
• Strong knowledge of creating Test Bench, Static Timing Analysis, ASIC Design flow, CMOS Logic Design.  
• Understanding of Caches Coherence Protocol (MESI), SoC Integration, Semiconductor Device, and Physics.
• Knowledge of DFT implementation and Scan insertion, ATPG, Logic BIST.
• Good team player with excellent communication skills.
• Languages: Verilog HDL, System Verilog, UVM, C, C++, Java, Data Structures, Perl, Python.
• EDA Tools: Quartus II, MODELSIM, Synopsys Design Compiler Libero IDE, Oscilloscope, Logic Analyzer, Cadence Virtuoso, Cadence Encounter, NC Verilog, I Verilog, Synopsys VCS (Verilog Compiler Simulator), GTKWave, Synopsys Design Vision, Synplify Pro, UNIX Working Environment.
• M.S. in Electrical Engineering.

Vanu – Senior Layout Designer Engineer

• Proficient with SiGe process as IBM bicmos 8hp, 9hp. TOWER-JAZZ bicmos Ha, H3, and TSMC process as 16 nano, 20 nano, 40, 60, 90 etc.
• Perform layout of high-speed VGA, TIA, LDO, OpAmp, Bias, Clamp, ADC, DAC, Power Generation, RF amplifiers, Detectors, Filters, Oscillators, etc.
• Module generated, synchronized clone with virtuoso up to date Cadence v6.16.
• High performance layout Electro migration, IR drop, ESD, Latchup.
• Ability to layout analog circuitry in a size/time constrained environment.

Juan – Mixed Signal Design Engineer  

• Extensive experience in Complex Analog and Mixed-signal circuit design & characterization.
• Great experience in RFIC circuits, matching and components in Transceiver.
• Thorough understanding in latest Process and Technology including FinFET.
• Strong experience in Mixed-Signal Verification/validation/SI and Integration.
• Working experience in Voltage Regulation, LDOs, Bandgaps, and Power Supply.
• Outstanding record in building new team, capability, and business.
• Efficient in developing CAD/PDK/FDK flows with Industry leading Cadence, Synopsys, and Mentor Graphics tools.
• Master of Engineering in Electrical Engineering.