Talent 101 Circuit

Jerry – Senior FPGA/ASIC Designer

• Logic design and verification, behavioral modeling and analog mixed-signal simulation and debug skills. Expertise in Verilog and VHDL coding, functional verification, synthesis, timing analysis, and micro architecture. Wrote and ran regression tests using TCL.
• Wrote VHDL and Verilog for DSP libraries and simulated these functions using MODELSIM.
• Wrote Perl programs to run all the VHDL and Verilog simulations.
• Logic Design/Verification (15 yrs.), RTL coding (10 yrs.), Verilog (10 yrs.), VHDL (10 yrs.).
• Analog Mixed-signal Simulation (Using SPICE and ModelSim) (18 years), UNIX (14 yrs.).

Shima – Senior IC Layout Design Engineer 

• Lead, schedule and plan circuit projects that are both efficient and cost effective within time scheduled
• Supervised and instruct team members through all phases of project
• Created layout that can and will save silicon waste and dollars
• Created the tightest compaction of layout possible
• Performed layout of Analog and Digital circuits in 250nm, 180nm, 130nm, 90nm, 65nm, 45nm, 40nm, 28nm and 10nm/finfet technologies
• Performed layout of RF/Analog circuits

Barbara – Senior ASIC Physical Design Engineer 

• 20+ years as a physical designer and 10 tape-outs, from netlist to GDS
• 10+ years of methodology development, understanding and using other company’s methodology
• VLSI design work & custom layout using backend tools from Synopsys(ICC1), Cadence(Innovus)
• Large 28 million gate design, physical partition into three blocks. Intel 10nm process and library and IP
• Create and developed a power estimate to create IR/EM correct power rails using Synopsys tools for TSMC flow
• Extensive use of portable scripting languages for tools flow development
• Versed in Microsoft EXCEL spreadsheet for calculations

Harold – Senior Design Verification Engineer

• Design Verification – Constrained Random Full Chip & Unit Level SoC, ASIC, & FPGA
• System Verilog/UVM
• Functional Coverage & Code Coverage
• Assertion (SVA) Based Verification
• Verilog, VHDL
• VCS, IUS, QuestaSim, Verdi
• Python, TCL & PERL Scripting
• VERA/RVM
• Test Bench Architecture & Implementation

Chang – Design Verification Engineer

• High-performance IC/ASIC design and verification.  
• Co-author of two patents.  Strong critical thinking, problem-solving, and planning skills.
• Expert in UVM, System Verilog, VHDL. 
• Experienced in developing and deploying new verification methodologies. 
• Proven track record of developing and delivering high-quality designs on time. 
• Strong leadership and collaboration skills.
• Outstanding team player, mentor, and coach.
• Engineering & Product Management.

Jeffrey – Design Verification Engineer

• Extensive experience in the Design Verification in both block and SoC levels 
• Skilled in directed and constrained-random test benches
• Proficient in Object-Oriented programming
• Languages – System Verilog, Verilog, SVA, C, Perl, Shell Scripts, assembly (e200, e500, HC08, HC12)
• Verification methodologies – UVM, VMM
• Simulators – VCS, NC Verilog (incisive), Verilog XL

Maribel – Senior ASIC/SOC Design/Verification Engineer 

• ASIC Firmware/Hardware Integration
• ASIC / SOC Development & Design & Methodology implementation
• Experienced project lead in hard drive controller support.
• ASIC/SOC Conceptual & Layout Design
• Verilog, VDHL, Perl, RTL, UNIX, embedded coding; some OOP C++ and Python.
• Drove/supported clock Generator, SOC Clock Timing, and IDDQ analysis.
• CPU and microarchitectures

Sostenes – FPGA Design Engineer

• 8 Years of strong experience in FPGA/ASIC design and verification flow, Architecture, RTL coding, Functional Verification, Synthesis, Gate level simulations, Static timing analysis (STA), ATPG
• Experience in the design of Xilinx Zynq-7000 Soc, Spartan3E, Lattice LFXP2-40E, and LFXP2-30E & Altera Cyclone III FPGA Boards
• Good Knowledge of ASIC design tools and process flow
• Proficient with C/C++, Verilog HDL, VHDL and System Verilog
• Good knowledge of simulation tools Cadence, Questasim, & Active 

Scree – Physical Design Engineer [Available April 15, 2018]

• 5 years’ experience
• Floor planning, placement, Clock Tree Synthesis, Routing
• Physical optimization - timing, power, area
• Static Timing Analysis signoff, power analysis
• Physical hardening of complex sub-designs
• Top level design planning, I/O placements, and full-chip closure.
• Signal integrity analysis
• Design Rule checks, Logic equivalence checks
• Design automation using scripting language

Kumar – Senior VLSI Engineer [Available May 1, 2018]

• 7yrs overall industry experience – IP verification (RTL and GLS), FPGA verification and RTL Design.
• Experience in Digital Verification (testbench environment, models, checkers, drivers, functional coverage, assertions and test case development in system Verilog and Verilog languages).
• Experience in using scripting languages like Perl for pre/post-processing of results.
• Experience in Verilog, SV and UVM test bench environments.
• Experience in RTL design.
• Experience in different serial and parallel bus protocols.