Talent 101 Circuit

IC Layout Engineer with 10+ years of experience

Posted on February 06, 2020 by Nick Trompert

Tom– IC Layout Engineer 

  • 10+ years of experience with IC Layout and IC Verification increasing responsibilities in the employment services to the EDA industry. 
  • Mentor Graphics tools: Pyxis, Calibre DRC/LVS, calibredrv, Ample, Design Manager-IC.
  • Tanner tools: L-Edit, Tanner-Calibre integration, Tanner LVS.
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Analytical and Resourceful Senior IC Layout Engineer  

Posted on July 19, 2019 by Nick Trompert

Samuel – Senior IC Layout Engineer  

  • Solid history of establishing and maintaining positive working relationships with Design, Product and Test Engineers
  • Analytical and resourceful in solving new and challenging problems 
  • Self-motivated individual contributor and positive team player  
  • Goal-directed with focus on details and follow-through
  • Cadence Virtuoso and VXL
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Circuit Design/Layout Engineer

Posted on June 07, 2019 by Nick Trompert

Rene – Circuit Design/Layout Engineer

  • CMOS Digital 16x16 crossbar switch - Tools: Cadence Virtuoso
  • Designed a digital switch using 16:1 multiplexer and 64-bit shift register on IBM 180 nm CMOS technology
  • Performed DRC, LVS and parasitic extraction along with post-layout simulation for the PCB layout of the circuit
  • Achieved an overall speed of 22.93 GHz for the entire circuit
  • Datapath synchronous controller design - Tools: Altera Quartus II
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Senior Layout Engineer and Certified PCB designer

Posted on May 24, 2019 by Nick Trompert

Keya – Senior Layout Engineer

  • Design Bureau Principal.
  • Program & CAE/CAD department manager.
  • Schematic/verification/physical layout of mixed signal CMOS Imager designs.
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Layout Engineer

Posted on April 03, 2019 by Nick Trompert

Vidal – Layout Engineer  

  • Perform chip level physical Analog Custom Layout design using latest Cadence Virtuoso Layout Editor VLE/VXL layout tools and techniques for optimization of speed, power, and area (.35um & .7um technologies).
  • Excellent device matching techniques along with debug and verification ability at device, cell, block, and chip levels.
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Senior Analog RF Layout Design Engineer

Posted on February 27, 2019 by Nick Trompert

Sophia – Senior Analog RF Layout Design Engineer

  • Cadence Virtuoso 6.1.7 Open Access, Cadence GXL/VXL, Cadence Diva, Cadence Dracula

  • Cadence Assura for LVS/DRC/Parasitic Extraction

  • Cadence VCR, Cadence P-Cell Creation, Cadence Multiple Part Path

  • Cadence Shape-Based Router (CSR) Cadence Space-Based Router

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Layout Engineer

Posted on February 12, 2019 by Nick Trompert

Wyatt – Layout Engineer

  • Senior R&D Lead Mask Layout Design Consultant

  • RF High Speed Analog Mixed Signal design

  • Full custom designed Analog Switching Regulator

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Senior Layout Engineer

Posted on January 29, 2019 by Nick Trompert

Maria– Senior Layout Engineer  

  • Senior IC Layout Designer/Leader with strong people, team-building, and project management skills

  • Lead Layout Designer, for new Rad Hard Microwave 10GHZ designs.

  • Utilizing SiGe IBM, HP for RF circuitry (TX, RX) etc

  • Created various IP in 45nm blocks

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Circuit Design/Layout Engineer

Posted on January 24, 2019 by Nick Trompert

Rene – Circuit Design/Layout Engineer

  • CMOS Digital 16x16 crossbar switch - Tools: Cadence Virtuoso

  • Designed a digital switch using 16:1 multiplexer and 64-bit shift register on IBM 180 nm CMOS technology

  • Performed DRC, LVS and parasitic extraction along with post-layout simulation for the PCB layout of the circuit

  • Achieved an overall speed of 22.93 GHz for the entire circuit

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Analog Layout Engineer (Available 12-15-2018)

Posted on December 12, 2018 by Nick Trompert

Suf – Analog Layout Engineer

  • Tope and Block Level Layout experience for Analog & Mixed Signal Technology

  • Cadence Tools

Processes:

  • LBC7, LBC8, LBC8HV, LBC8LV, LBC9, LBC9PLV, LBC5, 50HPA07, HPE35, BICOMHD, 1033BCOM3zl, 118C021A, TSMC .18 um, 1P6M, TowerJazz TS18PM .18 um, CMOS and TowerJazz SBC18H3A1P6 SIGe, .35 um and .6 um customer  processes  and nanometer FINFET  processes.

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