Talent CIRCUIT | Layout Engineer (2)

Layout Design Engineer with skills in analog layout and RF design techniques

Posted on September 24, 2018 by Nick Trompert

Bonnie – Layout Design Engineer

Layout Design Engineer with extensive experience in all phases of microchip layout design and ability to work independently to meet aggressive deadlines
Strengths in analog layout, RF design techniques, including shielding, matching, common centroiding cross-coupling, interdigitation etc.
Effective Executive layouts from floor plan to tape out, enabling design engineers to analyze, simulate, and create design improvements in a synergistic and timely manner.

Senior PCB Designer/Layout Engineer with 10+ years of experience in PCB design

Posted on September 21, 2018 by Nick Trompert

Erlie – Senior PCB Designer/Layout Engineer

A solid Senior PCB Designer/Layout Engineer with over 10+ years’ experience in PCB design, including 9 years for an industry leading semiconductor company and 8 years for a global contract manufacturing company.
Recognized as a high-performing, energetic individual who integrates well as a key collaborator or as an individual contributor.
Principal strengths include the ability to quickly assess and implement critical design input, multitasking, meeting deadlines, managing “on the fly” engineering changes with minimal impact to schedule, and utilizing exceptional problem-solving abilities.

IC Layout Design Engineer with skills in team management

Posted on August 13, 2018 by Nick Trompert

Harry – IC Layout Design Engineer

Custom layout of cells, IP blocks, and chips; including, where appropriate, floor planning, power planning, Analog/Digital custom layout, physical verification, and extraction.
Place and Route of IP and at Chip Level; including floor planning, power planning and routing, Placement (based on one or more of the following Timing, Power, Clocks, Regions and Groups, Routing density), Clock tree synthesis, Custom Analog routing (Shielding, RC matching, and keep out areas), Detail routing, ECO, layout verification (DRC/ERC/LVS/Antenna/Density/LVL), and extraction.
Group management; Schedule, methodology, and standards development.

Senior Layout Engineer with Strong People, Team-building, and Project Management skills

Posted on July 30, 2018 by Nick Trompert

Maria– Senior Layout Engineer

Senior IC Layout Designer/Leader with strong people, team-building, and project management skills
Lead Layout Designer, for new Rad Hard Microwave 10GHZ designs.
Utilizing SiGe IBM,HP for RF circuitry (TX, RX) etc

Senior Layout Engineer with 12+ years of experience

Posted on July 18, 2018 by Nick Trompert

Tony – Sr. Layout Engineer

12+ years design experience utilizing single, double and multiple metal Analog/Digital CMOS and BiCMOS processes.
Layout tools include Cadence VXL and VIRTUOSO, Emerald OPAL, ICED, Mentor Graphics and AutoCAD.
Proficient with Calibre, Dracula and Cadence verification tools, UNIX, LINUX and Windows Operating systems. Experience with LBC7 & LBC9

Analog Layout Design Engineer with 10+ Years experience

Posted on March 21, 2018 by Kent Smith

Ali – Analog Layout Design Engineer

10+ years’ experience
Experience working on Optical, Voice and Memory chips
Experience with both Chip and Block level work
DAC, Controller, Bi-CMOS, CMOS, LDO, PLL, ADC
Global Foundries, TSMC, Xfab Processes

Layout Engineer with Chip-Level Analog Layout Design Experience

Posted on December 13, 2017 by Kent Smith

Vidal - Layout Engineer

Perform chip level physical Analog Custom Layout design using latest Cadence Virtuoso Layout Editor VLE/VXL layout tools and techniques for optimization of speed, power, and area (.35um & .7um technologies).
Excellent device matching techniques along with debug and verification ability at device, cell, block, and chip levels.
Verify correctness and integrity of layout using expert checking (hierarchical) skills using DIVA and Calibre for DRC/Extraction/LVS/ERC/Antenna Checks.

Layout Engineer Available

Posted on August 08, 2017 by Kent Smith

Janice – Analog AMS Layout Engineer

Created custom layouts for LDOs Power Controller, LFO, HFO, and REF_SYS.
Floorplan, module interconnect, power routing and quality assurance of top level blocks
Created custom high voltage layouts for Oscillators, Current References, Charge Pumps, Voltage Regulators and various other cells used in the Flash Charge Pump

IC Layout Engineer Experienced with Multiple Tools

Posted on April 27, 2017 by Kent Smith

Samuel – Senior IC Layout Engineer

Solid history of establishing and maintaining positive working relationships with Design, Product and Test Engineers
Analytical and resourceful in solving new and challenging problems
Self-motivated individual contributor and positive team player
Goal-directed with focus on details and follow-through
Cadence Virtuoso and VXL
Hercules (DRC, LVS, EMC)

Qualified IC Layout Engineer Available

Posted on April 24, 2017 by Kent Smith

Jun – IC Layout Engineer

Hands on experience with FPGA Design and Implementation, RTL Design and Verification, ASIC Design.
Hands on experience with Nexys 2 Spartan-3E FPGA Trainer Board and Mercury Development Board.
Excellent independent work on ASIC/ PD flow and hands on experience with RTL to GDS II flow.
Hands on experience with Floorplan, Power plan, Place & Route, CTS, STA and Timing Closure.

Talent 101 Circuit