Talent 101 Circuit

Wang – Design/Layout Engineer  

• Design/Layout Engineer with over 10 years’ experience dealing with the design/layout of analog and/or mixed signal products
• Design lead of Serial EEPROM (SPI/I2C) products which include analog (voltage/current references), and +16V (charge-pumps, regulators, level-shifting) circuit blocks
• Design lead of RTCC products (SPI/I2C) which include analog (voltage/current references), memory (EEPROM, SRAM), and +16V (charge-pumps, regulators, level-shifting) circuit blocks

Gopal – Senior Analog IC Layout Engineer

• Experienced Sr. Analog IC Layout Engineer with 10+ years analog/mixed signal layout and engineering tech experience, working on custom analog/mixed-signal IC layout designs using VirtuosoXL (version IC5.1&6.1), Composer schematics; and Calibre, Assura, Hercules, and Dracula for verification, with Star-RC for parasitic extractions.

Jian – IC Layout Engineer

• Good understanding of CMOS Design, circuit simulation, circuit board and basic gates like NAND, MUXs,FFs etc.
• Familiar with IPC-A-600,610,613 standards
• Strong hold on IC Fabrication processes like diffusion, oxidation, lithography, etching, PVD and CVD
• Excellent team player with good communication, presentation and organization skills
• VLSI:  CMOS Logic, Circuit simulation, Semiconductor Fabrication Processes, Layout design rules,Verilog/VHDL programming, Cadence Tool, RTL design flow, Combinational and Sequential circuit design.

Naveen - Analog Layout Engineer  

Base Band Filter (BBF): 

• Description: It amplifies difference of voltage.
• Targeted Technology: TSMC 90nm
• Role: Develop layout from schematic, floor plan, placement, routing and clean DRC, LVS and QRC.
  

Low Noise Amplifier (LNA):

• Description: LNA is an electronic amplifier that amplifies a very low-power signal without significantly degrading its signal-to-noise ratio.
• Targeted Technology: TSMC 90nm
• Role: Develop layout from schematic, floor plan, placement, routing and clean DRC, LVS and QRC.

Kumar – Layout Engineer

• Desigining custom TCell’s for layout using C language in various semiconductor process nodes ranging from 0.18um – 45nm.
• Layout of new memory IP’s in various semiconductor process using L-edit.
• Managing the layouts of existing memory IP’s and performing physical verification using Calibre.