Talent 101 Circuit

Lieu – Verification Engineer   

• 10+ years of experienced in digital design and verification.  
• Designed micro-controllers, protocol controllers (multi-channel HDLC, AMI), DRAM controller, DSP functions (IIR/FIR filters, digital gain blocks, companders, DTMF generator), uP interfaces, serial interfaces and JTAG interface. 
• Written high level functions/behavioral models of ISDN S/T analog interface, DSP functions of CODEC, DTMF generator, SBus, ISA bus and memory elements.

Bob – Analog Mixed Signal Design/Verification Engineer

• Design of Analog blocks for capacitive touch circuits.
• Analog-Mixed signal verification at chip level.
• Write, debug, and run test benches using Verilog-A/Verilog-AMS/System Verilog to verify both models and transistor-level circuits at all operating modes using the AMS-Designer environment.
• Design functional models for Buck, Boost, LDO, Load Switch, RCO, Rectifiers, Analog comparators, PLL, ADCs in Verilog-AMS/DMS.

Chang – AMS Verification Engineer  

• Verilog A

• Identify and log bugs

• Work with Design team to resolve issues

Fong – AMS Verification Engineer

• Creating Test Benches in Verilog/SysVerilog

• Verilog A

• Conduct Regression test and compare to spec

Haylo – Design Verification Engineer   

• Experience working with DSP processor
• Deep knowledge of digital communication protocols: I2C, I2S, SPI, UART
• Experience with FPGA based designs using Verilog
• Working knowledge of circuit simulations using SPICE simulator

Naty – Design Verification Engineer  

• Diligent and detail-oriented aerospace engineer with hands-on experience in mechanical design, systems engineering, testing, coding, and vehicle control and dynamics.
• Strong analytical and problem-solving skills with great work ethics and ability to work in fast-paced and highly-collaborative environments

Shellie – Design Verification Engineer   

• Design Verification (DV) Engineer brings the experience of repeated success in building UVM verification environments to verify complex semi-custom ASIC semiconductor designs.
• System Verilog, UVM, SVA, C, Specman-e, Shell, Perl, Python
• ARM AMBA:  AHB, AXI/ACE
• Ethernet, PCS, SATA, USB, PCIe

Julie – Verification Engineer

• Programming Languages:  Verilog, VHDL, System Verilog, UVM, C, C++, PERL, SHELL, Cadence SKILL scripting
• Operating Systems:  UNIX, Linux and Windows

Alezandro – Senior Digital Design/Verification Engineer  

• 10+ years’ experience with Verilog RTL design including nine years with System Verilog design and verification.
• Experienced in CMOS integrated circuit design/verification at RTL and transistor levels.
• Custom and RTL-based design/verification projects include: MIPS and ARM-based SoCs, X86 CPU, 8/16-bit microcontrollers, DSP processor and custom CMOS memory design (Flash, SRAM, and ROM).

Marilyn – Digital Verification Engineer

• Extensive knowledge of System on Chip Architecture with ARM/MIPS processors, AMBA subsystem design, IP design and Verification, system level synthesis, timing and DFT.
• Experience with Board level schematic design, Layout verification, Product level verification, Safety certifications and FMEA
• Hands on experience in lab with FPGA prototyping, debugging, functional verification and manufacturing support
• Worked on System Level Architecture and RTL for System on Chip with ARM9 core, 10/100 Ethernet, USB, DMA controller, Flash Controller, DES, I2C, UART and other sub modules to be used for an aerospace client. Performed System level verification of this SoC.