Talent CIRCUIT | Verification Engineer (3)

Digital Verification Engineer (Available Now)

Posted on June 15, 2018 by Nick Trompert

Joran – Digital Verification Engineer

System level tests with RGB image inputs to exercise DRAM controller and DMD serial link controller. Wrote Perl script to convert model output to RGB images. Debug DRAM and sequencer settings.
Testbench for ARM Cortex subsystem with AXI, AHB, TCM, APB bus, bridges, and peripherals. Wrote checkers and tests to exercise all the bridges and peripherals including SPI and OCP interface with SPECMAN.
Testplan for Parallel Flash Controller and wrote SPECMAN model of NAND flash memory. Tested program fetches and execution from ARM and uncovered functional bugs through Incisive RTL simulator.

Digital Verification Engineer with 7+ years of experience

Posted on June 06, 2018 by Nick Trompert

Kumar – Digital Verification Engineer

7 years of experience in VLSI as a Verification Engineer.
Experience in IP level and module level Verification by using SV-UVM and Verilog.
Understanding in various bus protocols like AXI-Lite, AHB, APB and other proprietary protocols.

Verification Engineer with experience in RF Circuits and Network Theory

Posted on May 07, 2018 by Kent Smith

Kyle – Verification Engineer

RF Circuits & Network Theory
Link budget, EVM
LNA, Mixer, Pa and Filters
Switch, Transmitter & Receivers
RF testing, troubleshooting, debugging, developing & automated test systems
PCBs test & repair, QA & QC

Senior Design Verification Engineer with experience in Mixed Signal Design

Posted on April 16, 2018 by Kent Smith

Harold – Senior Design Verification Engineer

Design Verification – Constrained Random Full Chip & Unit Level SoC, ASIC, & FPGA
System Verilog/UVM
Functional Coverage & Code Coverage
Assertion (SVA) Based Verification
Verilog, VHDL
VCS, IUS, QuestaSim, Verdi
Python, TCL & PERL Scripting
VERA/RVM
Test Bench Architecture & Implementation

Design Verification Engineer with experience in IC/ASIC design

Posted on April 13, 2018 by Kent Smith

Chang – Design Verification Engineer

High-performance IC/ASIC design and verification.
Co-author of two patents. Strong critical thinking, problem-solving, and planning skills.
Expert in UVM, System Verilog, VHDL.
Experienced in developing and deploying new verification methodologies.
Proven track record of developing and delivering high-quality designs on time.
Strong leadership and collaboration skills.
Outstanding team player, mentor, and coach.
Engineering & Product Management.

Design Verification Engineer with Experience in block and SOC (Available Now)

Posted on April 06, 2018 by Kent Smith

Jeffrey – Design Verification Engineer

Extensive experience in the Design Verification in both block and SoC levels
Skilled in directed and constrained-random test benches
Proficient in Object-Oriented programming
Languages – System Verilog, Verilog, SVA, C, Perl, Shell Scripts, assembly (e200, e500, HC08, HC12)
Verification methodologies – UVM, VMM
Simulators – VCS, NC Verilog (incisive), Verilog XL

Senior ASIC/SOC Design & Verification Engineer Available Now

Posted on April 04, 2018 by Kent Smith

Maribel – Senior ASIC/SOC Design/Verification Engineer

ASIC Firmware/Hardware Integration
ASIC / SOC Development & Design & Methodology implementation
Experienced project lead in hard drive controller support.
ASIC/SOC Conceptual & Layout Design
Verilog, VDHL, Perl, RTL, UNIX, embedded coding; some OOP C++ and Python.
Drove/supported clock Generator, SOC Clock Timing, and IDDQ analysis.
CPU and microarchitectures

ASIC/FPGA Design Engineer with 8+ Years of Strong Experience Available

Posted on April 02, 2018 by Kent Smith

Sostenes – FPGA Design Engineer

8 Years of strong experience in FPGA/ASIC design and verification flow, Architecture, RTL coding, Functional Verification, Synthesis, Gate level simulations, Static timing analysis (STA), ATPG
Experience in the design of Xilinx Zynq-7000 Soc, Spartan3E, Lattice LFXP2-40E, and LFXP2-30E & Altera Cyclone III FPGA Boards
Good Knowledge of ASIC design tools and process flow
Proficient with C/C++, Verilog HDL, VHDL and System Verilog
Good knowledge of simulation tools Cadence, Questasim, & Active

Design Verification Engineer with experience in UVM

Posted on March 30, 2018 by Kent Smith

Samantha – Design Verification Engineer

Design Verification Engineer with experience in defining testbench architecture, verification planning, and implementation in UVM.
Knowledge of UVM Environment - Agents (Sequencer, Driver, Monitor), test writing/debug and Coverage.
Formal Verification, Assertion-based verification.
Strong knowledge of developing Stimulus, Verification flow, Digital Design, UVM, and OOP.
Proficient in developing Monitors, Checkers, and Scoreboards in System Verilog.
Experience on UNIX/LINUX, PERL, Verilog.
Master of Science in Electrical Engineering

Senior Verification Engineer with 8+ Years Experience Available

Posted on January 31, 2018 by Kent Smith

Sham - Senior Verification Engineer

8yrs+ overall industry experience in Mixed Signal and Digital Verification
Experience in System Verilog and UVM, PSL, and SVA Assertions
Behavioral Modeling of Analog Modules in SV, VAMS, and VHDL
Model Vs. Spice Simulations, Analog Mixed Signal Co-Simulations
Verification of Sound wire, I2C, AHB, and DMA protocols
Functional and Code coverage Analysis

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