Talent CIRCUIT | Verification Engineer (4)

Experienced Design Verification Engineer Available

Posted on July 07, 2017 by Kent Smith

Extensive experience in the Design Verification at both block and SoC levels.
Skilled in directed and constrained-random test benches. Proficient in Object-Oriented programming.
Languages – System Verilog, Verilog, SVA, C, Perl, shell scripts, assembly (e200, e500, HC08, HC12).
Verification Methodologies – UVM, VMM.
Simulators – VCS, NC Verilog (Incisive), Verilog XL.

Posted on June 26, 2017 by Kent Smith

Posted on December 21, 2016 by Kent Smith

Experience in ASIC/FPGA Design and Verification, Computer Architecture, Synthesis, RTL Debug, Python, C.
Strong knowledge of creating Test Bench, Static Timing Analysis, ASIC Design flow, CMOS Logic Design.
Understanding of Caches Coherence Protocol (MESI), SoC Integration, Semiconductor Device, and Physics.
Knowledge of DFT implementation and Scan insertion, ATPG, Logic BIST.
Good team player with excellent communication skills.
Languages: Verilog HDL, System Verilog, UVM, C, C++, Java, Data Structures, Perl, Python.
EDA Tools: Quartus II, MODELSIM, Synopsys Design Compiler Libero IDE, Oscilloscope, Logic Analyzer, Cadence Virtuoso, Cadence Encounter, NC Verilog, I Verilog, Synopsys VCS (Verilog Compiler Simulator), GTKWave, Synopsys Design Vision, Synplify Pro, UNIX Working Environment.
M.S. in Electrical Engineering.

Posted on December 02, 2016 by Kent Smith

Digital and AMS verification of Battery management, Battery Charger, Power resources (LDO’s, DCDC’s, REFERENCE), ADC’s, Fuel Gauge, PMIC’s, storage devices, automotive devices.
Experience of Mixed Signal Verification of PMIC’s, storage devices.
SoC verification(C / Specman based), RTL, GATE Level at TOP Level.
Behavioral models development for the Analog blocks using VHDL.
Top Level mixed mode simulations for verifying Digital and Analog integration and analog block functionalities.

Posted on August 19, 2016 by Kent Smith

Verification Engineer with 15+ years of experience specializing in digital verification, functional validation, full chip simulations, System Verilog development, test bench development.

Posted on August 17, 2016 by Kent Smith

Design Verification (DV) Engineer with 9+ years of experience.
Strong understanding of ARM CortexM3/A9 based SoC/Sub System verification, Low power simulation, Gate Level Simulation, Coverage closure and Production Pattern Generation.

Posted on August 10, 2016 by Kent Smith

Excellent in VLSI design flow which includes RTL designing using Verilog, verification of it using System Verilog and physical implementation using IC and DC Complier.
Hands on experience with full custom IC design while designing a 64x32 SRAM Memory using Custom designer and verifying it through DRC and LVS checks.
C programming and a working knowledge of PERL.
Masters of Science in Embedded Electrical and Computer Systems.