Talent 101 Circuit

Sydney - Electrical Engineer   

• ASIC design experience in taking designs from the preliminary netlist step through tape out.
• ASIC/FPGA development skills including: logic simulation, formal verification, static timing analysis, floor planning, place and route, timing closure, test vector generation, power analysis, signal integrity checks, LVS/DRC checks, limited logic synthesis and overall EDA methodology/flow compatibility issues.

Jian – IC Layout Engineer

• Good understanding of CMOS Design, circuit simulation, circuit board and basic gates like NAND, MUXs,FFs etc.
• Familiar with IPC-A-600,610,613 standards
• Strong hold on IC Fabrication processes like diffusion, oxidation, lithography, etching, PVD and CVD
• Excellent team player with good communication, presentation and organization skills
• VLSI:  CMOS Logic, Circuit simulation, Semiconductor Fabrication Processes, Layout design rules,Verilog/VHDL programming, Cadence Tool, RTL design flow, Combinational and Sequential circuit design.

Rafa – Mechanical Engineer

• 2D/3D CAD(AutoCAD, Solidworks and ProE)
• Finite Element Analysis (ANSYS)
• Manufacturing
• Sheet Metal Design
• Geometric Dimensioning and Tolerance (GD&T)

George - Electrical Engineer  

Joaquin – Analog Design Engineer

• Excellent Analytical, Problem-solving, Communication and Time-Management skills
• Proven ability as an effective Multi-tasker and a leader having strong Customer Service skills.
• Excellent object oriented programming skills and experience in working on UNIX and Linux environments.
• One-year hands-on experience with Digital Logic Design, Computer Architecture, FSM and Verilog RTL
• Two years of experience in designing Analog/Mixed Signal and RF Circuits using Cadence Virtuoso

Adam – Senior Layout Designer

• Experienced in digital layout in areas such as microprocessor, Digital Signal Processor (DSP), System on a Chip (SoC), RAM, EPROM, and fully differential logic
• Experienced in analog layout in areas such as Comparators, Digital to Analog Converters (DAC), Phase Lock Loops (PLL), Bandgaps, and Voltage Regulators

Changpu – Characterization Engineer

• Developed and completed the following items for DC/DC Buck converter characterization and verification:
• Characterization Plan
• Used Cadence Capture/Allegro to Design the Schematic and Layout for Evaluation board
• Bench Hardware Setup
• LabVIEW GUI
• Failure Analysis on the Hardware

Sai - Analog Mixed Signal Design/Verification Engineer

• Design of Analog blocks for capacitive touch circuits.
• Analog-Mixed signal verification at chip level.
• Write, debug, and run test benches using Verilog-A/Verilog-AMS/System Verilog to verify both models and transistor-level circuits at all operating modes using the AMS-Designer environment.
• Design functional models for Buck, Boost, LDO, Load Switch, RCO, Rectifiers, Analog comparators, PLL, ADCs in Verilog-AMS/DMS.
• Integration of full chip and Top Level simulations for ICs with the Power Management and Wireless Battery Charging circuits.
• Create, debug, and run test benches to execute transistor-level performance verification over design corners using the Spectre circuit simulator.
• Mix and match of Verilog and Spice netlist in Chip Level Simulations.
• Master of Science – Electrical Engineering

Kent– Circuit System/Design Engineer  

• Power over Ethernet (PoE)
• Power over Data Lines (PoDL) integrated circuits
• Current-limited voltage source for PoDL detect circuit
• Sense chopper amplifier for PoE
• Design for satellite TV receiver set top box SOC

Kumar – Layout Engineer

• Desigining custom TCell’s for layout using C language in various semiconductor process nodes ranging from 0.18um – 45nm.
• Layout of new memory IP’s in various semiconductor process using L-edit.
• Managing the layouts of existing memory IP’s and performing physical verification using Calibre.