Talent 101 Circuit

Raheem – Mechanical Engineer

• Mechanical design of pressure vessel and heat exchanger per ASME section VIII (boiler and pressure vessel code) ant TEMA
• Strong FEA analysis background and project engineering
• Compress 2016
• DesignCalcs 2014
• AutoCAD 2004, Pro/E Wildfire 2.0, Solidworks, Catia V5

Jared – Component Design Engineer

• Electrical Efficiency
• Control Systems.
• Power Electronics
• Bioelectronics
• Voltage Regulators
• Power Systems
• Python Development

Juan – IC Design Engineer   

• Creative and competent IC design engineer capable of working as an individual contributor or working effectively within a team environment in the technical definition, design and validation of schedule driven mixed signal IP
• Extensive experience in the design, implementation and debug of ESD and latch-up tolerant networks and circuits
• Highly proficient in floor-planning of circuits, ESD/latch-up tolerant layout practices and analog layout techniques

Gopal – Senior Analog IC Layout Engineer

• Experienced Sr. Analog IC Layout Engineer with 10+ years analog/mixed signal layout and engineering tech experience, working on custom analog/mixed-signal IC layout designs using VirtuosoXL (version IC5.1&6.1), Composer schematics; and Calibre, Assura, Hercules, and Dracula for verification, with Star-RC for parasitic extractions.

Manchu – Validation Engineer

• Experienced developing tests on various ATE (Automated Test Equipment) for Semiconductor IC’s (Integrated Circuits)
• Performed analysis on design/production data, using 6 sigma, to determine the production worthiness of the test program(s)
• Implemented methods and procedures for testing the precision, and accuracy, of products

Sydney - Electrical Engineer   

• ASIC design experience in taking designs from the preliminary netlist step through tape out.
• ASIC/FPGA development skills including: logic simulation, formal verification, static timing analysis, floor planning, place and route, timing closure, test vector generation, power analysis, signal integrity checks, LVS/DRC checks, limited logic synthesis and overall EDA methodology/flow compatibility issues.

Jian – IC Layout Engineer

• Good understanding of CMOS Design, circuit simulation, circuit board and basic gates like NAND, MUXs,FFs etc.
• Familiar with IPC-A-600,610,613 standards
• Strong hold on IC Fabrication processes like diffusion, oxidation, lithography, etching, PVD and CVD
• Excellent team player with good communication, presentation and organization skills
• VLSI:  CMOS Logic, Circuit simulation, Semiconductor Fabrication Processes, Layout design rules,Verilog/VHDL programming, Cadence Tool, RTL design flow, Combinational and Sequential circuit design.

Rafa – Mechanical Engineer

• 2D/3D CAD(AutoCAD, Solidworks and ProE)
• Finite Element Analysis (ANSYS)
• Manufacturing
• Sheet Metal Design
• Geometric Dimensioning and Tolerance (GD&T)

George - Electrical Engineer  

Joaquin – Analog Design Engineer

• Excellent Analytical, Problem-solving, Communication and Time-Management skills
• Proven ability as an effective Multi-tasker and a leader having strong Customer Service skills.
• Excellent object oriented programming skills and experience in working on UNIX and Linux environments.
• One-year hands-on experience with Digital Logic Design, Computer Architecture, FSM and Verilog RTL
• Two years of experience in designing Analog/Mixed Signal and RF Circuits using Cadence Virtuoso